<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/amdgpu.h, branch v6.8</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v6.8</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v6.8'/>
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<updated>2024-02-15T19:18:43Z</updated>
<entry>
<title>drm/amd: Stop evicting resources on APUs in suspend</title>
<updated>2024-02-15T19:18:43Z</updated>
<author>
<name>Mario Limonciello</name>
<email>mario.limonciello@amd.com</email>
</author>
<published>2024-02-08T05:52:55Z</published>
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<id>urn:sha1:3a9626c816db901def438dc2513622e281186d39</id>
<content type='text'>
commit 5095d5418193 ("drm/amd: Evict resources during PM ops prepare()
callback") intentionally moved the eviction of resources to earlier in
the suspend process, but this introduced a subtle change that it occurs
before adev-&gt;in_s0ix or adev-&gt;in_s3 are set. This meant that APUs
actually started to evict resources at suspend time as well.

Explicitly set s0ix or s3 in the prepare() stage, and unset them if the
prepare() stage failed.

v2: squash in warning fix from Stephen Rothwell

Reported-by: Jürg Billeter &lt;j@bitron.ch&gt;
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3132#note_2271038
Fixes: 5095d5418193 ("drm/amd: Evict resources during PM ops prepare() callback")
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: make damage clips support configurable</title>
<updated>2024-02-15T19:18:42Z</updated>
<author>
<name>Hamza Mahfooz</name>
<email>hamza.mahfooz@amd.com</email>
</author>
<published>2024-02-08T21:23:29Z</published>
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<id>urn:sha1:d16df040c8dad25c962b4404d2d534bfea327c6a</id>
<content type='text'>
We have observed that there are quite a number of PSR-SU panels on the
market that are unable to keep up with what user space throws at them,
resulting in hangs and random black screens. So, make damage clips
support configurable and disable it by default for PSR-SU displays.

Cc: stable@vger.kernel.org
Reviewed-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Signed-off-by: Hamza Mahfooz &lt;hamza.mahfooz@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: skip to program GFXDEC registers for suspend abort</title>
<updated>2024-02-07T23:19:04Z</updated>
<author>
<name>Prike Liang</name>
<email>Prike.Liang@amd.com</email>
</author>
<published>2024-01-16T11:10:45Z</published>
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<id>urn:sha1:93bafa32a6918154aa0caf9f66679a32c2431357</id>
<content type='text'>
In the suspend abort cases, the gfx power rail doesn't turn off so
some GFXDEC registers/CSB can't reset to default value and at this
moment reinitialize GFXDEC/CSB will result in an unexpected error.
So let skip those program sequence for the suspend abort case.

Signed-off-by: Prike Liang &lt;Prike.Liang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add debug flag to place fw bo on vram for frontdoor loading</title>
<updated>2024-01-15T23:32:49Z</updated>
<author>
<name>Le Ma</name>
<email>le.ma@amd.com</email>
</author>
<published>2024-01-09T09:44:39Z</published>
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<id>urn:sha1:d20e1aec8862e48a352ca86969cee6f530dd41d5</id>
<content type='text'>
Use debug_mask=0x8 param to help isolating data path issues
on new systems in early phase.

v2: rename the flag for explicitness (lijo)

Signed-off-by: Le Ma &lt;le.ma@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>Revert "drm/amdgpu: add param to specify fw bo location for front-door loading"</title>
<updated>2024-01-15T23:32:23Z</updated>
<author>
<name>Le Ma</name>
<email>le.ma@amd.com</email>
</author>
<published>2024-01-09T04:06:25Z</published>
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<id>urn:sha1:6c5683bd9ecaa7f199c3122c1010ece5d59b1aef</id>
<content type='text'>
This reverts commit c572abffe9f50c8ba33060865449313b3f588c35.

Will use debug module param instead of independent module param.

Signed-off-by: Le Ma &lt;le.ma@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add param to specify fw bo location for front-door loading</title>
<updated>2024-01-05T21:10:43Z</updated>
<author>
<name>Le Ma</name>
<email>le.ma@amd.com</email>
</author>
<published>2024-01-03T07:27:38Z</published>
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<id>urn:sha1:c572abffe9f50c8ba33060865449313b3f588c35</id>
<content type='text'>
This param can help isolating data path issues on new systems in early phase.

Signed-off-by: Le Ma &lt;le.ma@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Enable tunneling on high-priority compute queues</title>
<updated>2023-12-13T20:23:59Z</updated>
<author>
<name>Friedrich Vock</name>
<email>friedrich.vock@gmx.de</email>
</author>
<published>2023-12-02T00:17:40Z</published>
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<id>urn:sha1:91963397c49aa2907aeafa52d929555dcbc9cd07</id>
<content type='text'>
This improves latency if the GPU is already busy with other work.
This is useful for VR compositors that submit highly latency-sensitive
compositing work on high-priority compute queues while the GPU is busy
rendering the next frame.

Userspace merge request:
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26462

v2: bump driver version (Alex)

Reviewed-by: Marek Olšák &lt;marek.olsak@amd.com&gt;
Signed-off-by: Friedrich Vock &lt;friedrich.vock@gmx.de&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/pm: setup the framework to support Wifi RFI mitigation feature</title>
<updated>2023-12-13T20:23:50Z</updated>
<author>
<name>Evan Quan</name>
<email>quanliangl@hotmail.com</email>
</author>
<published>2023-12-11T10:06:27Z</published>
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<id>urn:sha1:b8b39de646274366d17a3614fdaf65fa0716ab32</id>
<content type='text'>
With WBRF feature supported, as a driver responding to the frequencies,
amdgpu driver is able to do shadow pstate switching to mitigate possible
interference(between its (G-)DDR memory clocks and local radio module
frequency bands used by Wifi 6/6e/7).

--
v1-&gt;v2:
  - update the prompt for feature support(Lijo)
v8-&gt;v9:
  - update parameter document for smu_wbrf_event_handler(Simon)
v9-&gt;v10:
v10-&gt;v11:
 - correct the logics for wbrf range sorting(Lijo)
v13:
 - Fix the format issue (IIpo Jarvinen)

Signed-off-by: Evan Quan &lt;quanliangl@hotmail.com&gt;
Reviewed-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Signed-off-by: Ma Jun &lt;Jun.Ma2@amd.com&gt;
Signed-off-by: Ma Jun &lt;Jun.Ma2@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add amdgpu_reg_state.h</title>
<updated>2023-11-29T21:49:24Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2023-09-13T16:00:44Z</published>
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<id>urn:sha1:9a5095e785c38ab8d9f3d91f4ee76f4f73ec4adc</id>
<content type='text'>
This header defines the reg state structures exposed via
sysfs for umr debugging.

v2: add content type

Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd: Document device reset methods</title>
<updated>2023-11-29T21:23:31Z</updated>
<author>
<name>André Almeida</name>
<email>andrealmeid@igalia.com</email>
</author>
<published>2023-11-10T17:23:28Z</published>
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<id>urn:sha1:613ecd6563d2716192e69624105fe1939d104663</id>
<content type='text'>
Document what each amdgpu driver reset method does.

Signed-off-by: André Almeida &lt;andrealmeid@igalia.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
