<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c, branch v6.7</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v6.7</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v6.7'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2023-08-31T22:09:45Z</updated>
<entry>
<title>drm/amdgpu: Support query ecc cap for aqua_vanjaram</title>
<updated>2023-08-31T22:09:45Z</updated>
<author>
<name>Hawking Zhang</name>
<email>Hawking.Zhang@amd.com</email>
</author>
<published>2023-08-23T09:43:46Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=e0c5c387ac608591c1ce60383b43a99b261483de'/>
<id>urn:sha1:e0c5c387ac608591c1ce60383b43a99b261483de</id>
<content type='text'>
Driver queries umc_info v4_0 to identify ecc cap
for aqua_vanjaram

Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Candice Li &lt;candice.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/atomfirmware: Clean up errors in amdgpu_atomfirmware.c</title>
<updated>2023-08-09T13:43:23Z</updated>
<author>
<name>Ran Sun</name>
<email>sunran001@208suo.com</email>
</author>
<published>2023-08-02T06:51:27Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=7163dadea2cc0746bf29e93a65949d532a40a907'/>
<id>urn:sha1:7163dadea2cc0746bf29e93a65949d532a40a907</id>
<content type='text'>
Fix the following errors reported by checkpatch:

ERROR: spaces required around that '&gt;=' (ctx:WxV)
ERROR: spaces required around that '!=' (ctx:WxV)
ERROR: code indent should use tabs where possible

Signed-off-by: Ran Sun &lt;sunran001@208suo.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/atomfirmware: fix LPDDR5 width reporting</title>
<updated>2023-06-23T19:35:16Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2023-06-07T16:43:30Z</published>
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<id>urn:sha1:c09b3bf7363db982b17950b8e4f27b0564817301</id>
<content type='text'>
LPDDR5 channels are 32 bit rather than 64, report the width properly
in the log.

v2: Only LPDDR5 are 32 bits per channel.  DDR5 is 64 bits per channel

Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2468
Acked-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add new vram type for dgpu</title>
<updated>2023-06-09T13:44:25Z</updated>
<author>
<name>Hawking Zhang</name>
<email>Hawking.Zhang@amd.com</email>
</author>
<published>2022-05-27T05:47:24Z</published>
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<id>urn:sha1:cd8d77f328c53aad8915c9c4d64cf557742bb257</id>
<content type='text'>
hbm3 will be supported in some dgpu program

Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Le Ma &lt;Le.Ma@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: skip vram reserve on firmware_v2_2 for bare-metal</title>
<updated>2022-11-29T16:03:36Z</updated>
<author>
<name>Likun Gao</name>
<email>Likun.Gao@amd.com</email>
</author>
<published>2022-11-23T09:49:28Z</published>
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<id>urn:sha1:c0924ad731a8bbff14b5c733a87f572b000b290c</id>
<content type='text'>
vram_usagebyfirmware v2_2 is only used in SRIOV case, skip the related
settings in bare-metal case currently.

Signed-off-by: Likun Gao &lt;Likun.Gao@amd.com&gt;
Reviewed-by: Feifei Xu &lt;Feifei.Xu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add drv_vram_usage_va for virt data exchange</title>
<updated>2022-11-29T16:03:35Z</updated>
<author>
<name>Tong Liu01</name>
<email>Tong.Liu01@amd.com</email>
</author>
<published>2022-11-17T10:18:58Z</published>
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<id>urn:sha1:6d96ced7600e02ac1efb03a21af529fd9a95e3c6</id>
<content type='text'>
For vram_usagebyfirmware_v2_2, fw_vram_reserve is not used. So
fw_vram_usage_va is NULL, and cannot do virt data exchange
anymore. Should add drv_vram_usage_va to do virt data exchange
in vram_usagebyfirmware_v2_2 case. And refine some code style
checks in pre add vram reservation logic patch

Signed-off-by: Tong Liu01 &lt;Tong.Liu01@amd.com&gt;
Acked-by: Luben Tuikov &lt;luben.tuikov@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add vram reservation based on vram_usagebyfirmware_v2_2</title>
<updated>2022-11-10T20:29:40Z</updated>
<author>
<name>Tong Liu01</name>
<email>Tong.Liu01@amd.com</email>
</author>
<published>2022-11-10T09:31:36Z</published>
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<id>urn:sha1:4864f2ee9ee2acf4a1009b58fbc62f17fa086d4e</id>
<content type='text'>
Move TMR region from top of FB to 2MB for FFBM, so we need to
reserve TMR region firstly to make sure TMR can be allocated at 2MB

Signed-off-by: Tong Liu01 &lt;Tong.Liu01@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: change vram width algorithm for vram_info v3_0</title>
<updated>2022-08-10T18:59:04Z</updated>
<author>
<name>Likun Gao</name>
<email>Likun.Gao@amd.com</email>
</author>
<published>2022-08-03T04:16:35Z</published>
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<id>urn:sha1:4a0a2cf4c03ba49a4c2596c49c7daa719917d509</id>
<content type='text'>
Update the vram width algorithm for vram_info v3_0 to align with the
changes of latest IFWI.

Signed-off-by: Likun Gao &lt;Likun.Gao@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org # 5.19.x
</content>
</entry>
<entry>
<title>drm/amdgpu: differentiate between LP and non-LP DDR memory</title>
<updated>2022-05-26T18:56:33Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2022-05-23T15:24:31Z</published>
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<id>urn:sha1:d534ca7128d7bf681ed6d462c09b9d6ffb3bed91</id>
<content type='text'>
Some applications want to know whether the memory is LP or
not.

Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: query core refclk from bios for smu v13</title>
<updated>2022-05-04T13:57:35Z</updated>
<author>
<name>Hawking Zhang</name>
<email>Hawking.Zhang@amd.com</email>
</author>
<published>2022-01-23T11:12:30Z</published>
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<id>urn:sha1:f0b0a1b8062dba25cfe632582c92c047242598b2</id>
<content type='text'>
The smu_info structrue for smu v13 is changed that
core_refclk in v31 strucuture is not correct for
smu v13_0_0

Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Likun Gao &lt;Likun.Gao@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
