<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c, branch v5.3</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.3</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.3'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2019-08-26T20:33:36Z</updated>
<entry>
<title>drm/amdgpu: fix dma_fence_wait without reference</title>
<updated>2019-08-26T20:33:36Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2019-08-16T12:56:35Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=42068e1ef961c719f967dbbb4ddcb394a0ba7917'/>
<id>urn:sha1:42068e1ef961c719f967dbbb4ddcb394a0ba7917</id>
<content type='text'>
We need to grab a reference to the fence we wait for.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd: drop use of drmP.h in amdgpu/amdgpu*</title>
<updated>2019-06-10T21:02:48Z</updated>
<author>
<name>Sam Ravnborg</name>
<email>sam@ravnborg.org</email>
</author>
<published>2019-06-09T22:07:56Z</published>
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<id>urn:sha1:fdf2f6c56e5e289c7d7e726b676aba25643b39a0</id>
<content type='text'>
Drop use of drmP.h in all files named amdgpu*
in drm/amd/amdgpu/

Fix fallout.

Signed-off-by: Sam Ravnborg &lt;sam@ravnborg.org&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: "Christian König" &lt;christian.koenig@amd.com&gt;
Cc: "David (ChunMing) Zhou" &lt;David1.Zhou@amd.com&gt;
Cc: David Airlie &lt;airlied@linux.ie&gt;
Cc: Daniel Vetter &lt;daniel@ffwll.ch&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20190609220757.10862-10-sam@ravnborg.org
</content>
</entry>
<entry>
<title>drm/amdgpu: wait for VM to become idle during flush</title>
<updated>2019-03-19T20:36:58Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2019-01-10T15:48:23Z</published>
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<id>urn:sha1:56753e73fb2ed232278eb69445cb72c6f54391c2</id>
<content type='text'>
Make sure that not only the entities are flush, but that
we also wait for the HW to finish all processing.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: remove non-sense NULL ptr check</title>
<updated>2019-03-19T20:36:58Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2019-01-10T15:40:42Z</published>
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<id>urn:sha1:3119e7f43be172779019f282aed115b2ec0864fa</id>
<content type='text'>
It's a bug having a dead pointer in the IDR, silently returning
is the worst we can do.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add a new flag to AMDGPU_CTX_OP_QUERY_STATE2</title>
<updated>2019-03-19T20:36:51Z</updated>
<author>
<name>xinhui pan</name>
<email>xinhui.pan@amd.com</email>
</author>
<published>2018-12-17T06:31:12Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=ae363a212b145a0d4e0507e26e6c1b937181ec34'/>
<id>urn:sha1:ae363a212b145a0d4e0507e26e6c1b937181ec34</id>
<content type='text'>
Add AMDGPU_CTX_QUERY2_FLAGS_RAS_CE/UE which indicate if any error happened
between previous query and this query.

Signed-off-by: xinhui pan &lt;xinhui.pan@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Only add rqs for initialized rings.</title>
<updated>2019-02-15T16:15:30Z</updated>
<author>
<name>Bas Nieuwenhuizen</name>
<email>bas@basnieuwenhuizen.nl</email>
</author>
<published>2019-01-30T01:53:20Z</published>
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<id>urn:sha1:2a84e48e9712ea8591a10dd59d59ccab3d54efd6</id>
<content type='text'>
I don't see another way to figure out if a ring is initialized if
the hardware block might not be initialized.

Entities have been fixed up to handle num_rqs = 0.

Signed-off-by: Bas Nieuwenhuizen &lt;bas@basnieuwenhuizen.nl&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Limit vm max ctx number to 4096</title>
<updated>2018-12-10T20:21:13Z</updated>
<author>
<name>Rex Zhu</name>
<email>Rex.Zhu@amd.com</email>
</author>
<published>2018-10-24T08:10:33Z</published>
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<id>urn:sha1:08d1bdd4cc57e89d037205687a61d2b6ff9dddd4</id>
<content type='text'>
driver need to reserve resource for each ctx for
some hw features. so add this limitation.

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add VCN JPEG support amdgpu_ctx_num_entities</title>
<updated>2018-11-30T17:01:23Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2018-11-27T16:41:27Z</published>
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<id>urn:sha1:f52c96430f6bbdb088ed813af66588335052ec4d</id>
<content type='text'>
Looks like it was missed when setting support was added.

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: amdgpu_ctx_add_fence can't fail</title>
<updated>2018-08-27T20:12:10Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-08-24T12:23:33Z</published>
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<id>urn:sha1:85eff20020a656b2d13b33dc4681523508fee037</id>
<content type='text'>
No more waiting for a fence done here.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Reviewed-by: Junwei Zhang &lt;Jerry.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: rework ctx entity creation</title>
<updated>2018-08-27T16:11:11Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-08-01T14:00:52Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=1b1f2fecb699bb4ccc3cb2fafe92950e9bdb39de'/>
<id>urn:sha1:1b1f2fecb699bb4ccc3cb2fafe92950e9bdb39de</id>
<content type='text'>
Use a fixed number of entities for each hardware IP.

The number of compute entities is reduced to four, SDMA keeps it two
entities and all other engines just expose one entity.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
