linux/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c, branch v5.3

drm/amdgpu/psp: add a mutex to protect access to the psp ring

2019-07-09T22:43:39Z

We need to serialize access to the psp ring if there are multiple callers at runtime. Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher

drm/amdgpu: properly guard the generic discovery code

2019-07-09T22:43:31Z

It's only available on navi and newer. Reviewed-by: Xiaojie Yuan Signed-off-by: Alex Deucher

amdgpu: make pmu support optional

2019-07-08T18:56:22Z

When CONFIG_PERF_EVENTS is disabled, we cannot compile the pmu portion of the amdgpu driver: drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c:48:38: error: no member named 'hw' in 'struct perf_event' struct hw_perf_event *hwc = &event->hw; ~~~~~ ^ drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c:51:13: error: no member named 'attr' in 'struct perf_event' if (event->attr.type != event->pmu->type) ~~~~~ ^ ... Use conditional compilation for this file. Fixes: 9c7c85f7ea1f ("drm/amdgpu: add pmu counters") Signed-off-by: Arnd Bergmann Signed-off-by: Alex Deucher

drm/amdgpu: Disable ras features on all IPs before gpu reset

2019-07-05T20:59:20Z

Perform a ras_suspend to disable ras on all IPs to workaround some ROCm stability issue. Signed-off-by: xinhui pan Acked-by: Andrey Grodzovsky Signed-off-by: Alex Deucher

drm/amdgpu: enable PCIE atomics ops support

2019-07-01T19:54:40Z

GPU atomics operation depends on PCIE atomics support. Always enable PCIE atomics ops support in case that it hasn't been enabled. Signed-off-by: Jack Xiao Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher

drm/amdgpu: fix MGPU fan boost enablement for XGMI reset

2019-07-01T19:54:12Z

MGPU fan boost feature should not be enabled until all the devices from the same hive are all back from reset. Signed-off-by: Evan Quan Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

Merge branch 'drm-next' into drm-next-5.3

2019-06-25T13:42:25Z

Backmerge drm-next and fix up conflicts due to drmP.h removal. Signed-off-by: Alex Deucher

drm/amdgpu: Enable DC support for Navi10

2019-06-22T14:34:07Z

Enable the IP for navi10. Signed-off-by: Harry Wentland Signed-off-by: Alex Deucher

drm/amd/display: Read soc_bounding_box from gpu_info (v2)

2019-06-21T23:59:34Z

[WHY] We don't want to expose sensitive ASIC information before ASIC release. [HOW] Encode the soc_bounding_box in the gpu_info FW (for Linux) and read it at driver load. v2: fix warning when CONFIG_DRM_AMD_DC_DCN2_0 is not set (Alex) Signed-off-by: Harry Wentland Signed-off-by: Alex Deucher

drm/amdgpu: add to set navi ip blocks

2019-06-21T23:59:24Z

Set the IPs for navi10 in early_init like other asics. Signed-off-by: Huang Rui Reviewed-by: Alex Deucher Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher