<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c, branch v5.4</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.4</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.4'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2019-11-07T03:06:23Z</updated>
<entry>
<title>drm/amdgpu: register gpu instance before fan boost feature enablment</title>
<updated>2019-11-07T03:06:23Z</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2019-11-05T10:13:49Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=6a299d7aaa97dfde5988d8f9e2fa2c046b5793ff'/>
<id>urn:sha1:6a299d7aaa97dfde5988d8f9e2fa2c046b5793ff</id>
<content type='text'>
Otherwise, the feature enablement will be skipped due to wrong count.

Fixes: beff74bc6e0fa91 ("drm/amdgpu: fix a race in GPU reset with IB test (v2)")
Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Handle job is NULL use case in amdgpu_device_gpu_recover</title>
<updated>2019-08-30T20:02:39Z</updated>
<author>
<name>Andrey Grodzovsky</name>
<email>andrey.grodzovsky@amd.com</email>
</author>
<published>2019-08-27T16:14:47Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=0b2d2c2eecf27f403df60ebab06cad7b6bfe84f8'/>
<id>urn:sha1:0b2d2c2eecf27f403df60ebab06cad7b6bfe84f8</id>
<content type='text'>
This should be checked at all places job is accessed.

Signed-off-by: Andrey Grodzovsky &lt;andrey.grodzovsky@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Enable DC on Renoir</title>
<updated>2019-08-29T20:52:34Z</updated>
<author>
<name>Roman Li</name>
<email>Roman.Li@amd.com</email>
</author>
<published>2019-08-08T20:26:44Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=e1c14c43395c54c213a6bd415ba2db50fe503598'/>
<id>urn:sha1:e1c14c43395c54c213a6bd415ba2db50fe503598</id>
<content type='text'>
Enable DC support for renoir.

Acked-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Roman Li &lt;Roman.Li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: introduce vram lost for reset (v2)</title>
<updated>2019-08-29T20:52:32Z</updated>
<author>
<name>Monk Liu</name>
<email>Monk.Liu@amd.com</email>
</author>
<published>2019-08-27T08:32:55Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=e352625796b343cc85b7648a74a57e739b12dc27'/>
<id>urn:sha1:e352625796b343cc85b7648a74a57e739b12dc27</id>
<content type='text'>
for SOC15/vega10 the BACO reset &amp; mode1 would introduce vram lost
in high end address range, current kmd's vram lost checking cannot
catch it since it only check very ahead visible frame buffer

v2:
cover NV as well

Signed-off-by: Monk Liu &lt;Monk.Liu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Use new mode2 reset interface for RV.</title>
<updated>2019-08-15T16:00:44Z</updated>
<author>
<name>Andrey Grodzovsky</name>
<email>andrey.grodzovsky@amd.com</email>
</author>
<published>2019-07-26T18:07:42Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=c43b849f890af2b638b3bea79a4203875bcc54d7'/>
<id>urn:sha1:c43b849f890af2b638b3bea79a4203875bcc54d7</id>
<content type='text'>
Integrate the mode2 reset into rest sequence.

v2:
Check ppfuncs pointer for NULL

Signed-off-by: Andrey Grodzovsky &lt;andrey.grodzovsky@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Evan Quan &lt;evan.quan@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add renoir support for gpu_info and ip block setting</title>
<updated>2019-08-12T17:47:49Z</updated>
<author>
<name>Huang Rui</name>
<email>ray.huang@amd.com</email>
</author>
<published>2019-07-24T18:38:15Z</published>
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<id>urn:sha1:b51a26a02abe921e599971659e2177fd2c6a1e81</id>
<content type='text'>
This patch adds renoir support for gpu_info firmware and ip block setting.

Acked-by: Huang Rui &lt;ray.huang@amd.com&gt;
Signed-off-by: Huang Rui &lt;ray.huang@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add renoir asic_type enum</title>
<updated>2019-08-12T17:47:49Z</updated>
<author>
<name>Huang Rui</name>
<email>ray.huang@amd.com</email>
</author>
<published>2019-07-24T18:36:09Z</published>
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<id>urn:sha1:1eee4228a583b20082367e5cdce403bbdad2d7f1</id>
<content type='text'>
This patch adds renoir to amd_asic_type enum and amdgpu_asic_name[].

Acked-by: Huang Rui &lt;ray.huang@amd.com&gt;
Signed-off-by: Huang Rui &lt;ray.huang@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: remove RREG64/WREG64</title>
<updated>2019-08-09T16:17:30Z</updated>
<author>
<name>Tao Zhou</name>
<email>tao.zhou1@amd.com</email>
</author>
<published>2019-08-09T07:57:51Z</published>
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<id>urn:sha1:6ca523d7eb198b78f79df882b7dc4a8c795d8777</id>
<content type='text'>
atomic 64 bits REG operations are useless currently

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Tao Zhou &lt;tao.zhou1@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: replace readq/writeq with atomic64 operations</title>
<updated>2019-08-09T16:14:11Z</updated>
<author>
<name>Tao Zhou</name>
<email>tao.zhou1@amd.com</email>
</author>
<published>2019-08-07T02:28:54Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=c6dddf45402caeadc49dc859fa497cfb98841af4'/>
<id>urn:sha1:c6dddf45402caeadc49dc859fa497cfb98841af4</id>
<content type='text'>
what we really want is a read or write that is guaranteed to be 64 bits
at a time, atomic64 operations are supported on all architectures

Signed-off-by: Tao Zhou &lt;tao.zhou1@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Fix GPU reset crash regression.</title>
<updated>2019-08-06T18:53:19Z</updated>
<author>
<name>Andrey Grodzovsky</name>
<email>andrey.grodzovsky@amd.com</email>
</author>
<published>2019-08-02T20:48:08Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=b5507c7e06076d874923aa958ddb8829e3cfc573'/>
<id>urn:sha1:b5507c7e06076d874923aa958ddb8829e3cfc573</id>
<content type='text'>
amdgpu_ip_block.status.hw for GMC wasn't set to
false on suspend during GPU reset and so on resume gmc_v9_0_resume
wasn't called.
Caused by 'drm/amdgpu: fix double ucode load by PSP(v3)'

Signed-off-by: Andrey Grodzovsky &lt;andrey.grodzovsky@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
