<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c, branch v4.6</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v4.6</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v4.6'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2016-04-01T14:08:39Z</updated>
<entry>
<title>drm/amdgpu: fence wait old rcu slot</title>
<updated>2016-04-01T14:08:39Z</updated>
<author>
<name>Chunming Zhou</name>
<email>David1.Zhou@amd.com</email>
</author>
<published>2016-03-31T03:07:14Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=fc387a0b183150b5beb953d740441f19b49a1fb3'/>
<id>urn:sha1:fc387a0b183150b5beb953d740441f19b49a1fb3</id>
<content type='text'>
since the rcu slot was initialized to be num_hw_submission,
if command submission doesn't use scheduler, this limitation
will be invalid like uvd test.

Signed-off-by: Chunming Zhou &lt;David1.Zhou@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: switch back to 32bit hw fences v2</title>
<updated>2016-03-16T22:00:10Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2016-03-14T14:46:06Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=742c085fa86345ae9de259c7f15c652322da4e83'/>
<id>urn:sha1:742c085fa86345ae9de259c7f15c652322da4e83</id>
<content type='text'>
We don't need to extend them to 64bits any more, so avoid the extra overhead.

v2: update commit message.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: remove amdgpu_fence_is_signaled</title>
<updated>2016-03-16T22:00:01Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2016-03-14T14:23:11Z</published>
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<id>urn:sha1:480d0bf07ecf27da0a5f12774d9642072c364fa9</id>
<content type='text'>
It's just overhead to check the fence value
when we signal them directly anyway.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: drop the extra fence range check v2</title>
<updated>2016-03-16T21:59:52Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2016-03-14T13:49:33Z</published>
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<id>urn:sha1:91cc6418a0ea14633bdc1d2ea91d174fc1e9187d</id>
<content type='text'>
Amdgpu doesn't support using scratch registers for fences any more.
So we won't see values like 0xdeadbeef as fence value any more.

v2: reschedule timer even if no change detected

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: signal fences directly in amdgpu_fence_process</title>
<updated>2016-03-16T21:59:41Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2016-03-14T13:29:46Z</published>
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<id>urn:sha1:4a7d74f1763edd96badba1fe1c99f07ddf0376a6</id>
<content type='text'>
Because of the scheduler we need to signal all fences immediately
anyway, so try to avoid the waitqueue overhead.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: cleanup amdgpu_fence_wait_empty v2</title>
<updated>2016-03-16T21:59:32Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2016-03-13T18:37:01Z</published>
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<id>urn:sha1:f09c2be4d4804963f18417abd5b51bc8a8330851</id>
<content type='text'>
Just wait for last fence instead of waiting for the sequence manually.

v2: don't use amdgpu_sched_jobs for the mask

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: keep all fences in an RCU protected array v2</title>
<updated>2016-03-16T21:59:22Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2016-03-13T18:19:48Z</published>
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<id>urn:sha1:c89377d10a11e5d8be11525f220dc624574c1aa5</id>
<content type='text'>
Just keep all HW fences in a RCU protected array as a
first step to replace the wait queue.

v2: update commit message, move fixes into separate patch.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add number of hardware submissions to amdgpu_fence_driver_init_ring</title>
<updated>2016-03-16T21:59:12Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2016-03-15T13:52:26Z</published>
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<id>urn:sha1:e6151a08bbb3c85cd0b23813432690939e143131</id>
<content type='text'>
Make this a parameter instead of using the global variable directly.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: RCU protected amdgpu_fence_release</title>
<updated>2016-03-16T21:58:52Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2016-03-15T12:40:17Z</published>
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<id>urn:sha1:b44135351a3a5cfc60f5b6729445311c2d5e141c</id>
<content type='text'>
Fences must be freed RCU protected, otherwise the reservation_object_*_rcu()
functions can run into problems.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: merge amdgpu_fence_process and _activity</title>
<updated>2016-03-16T21:58:43Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2016-03-11T16:57:56Z</published>
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<id>urn:sha1:ca08e04d5642c429ec891fa17bf379be988dea6b</id>
<content type='text'>
No need to keep the two separate any more.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
</content>
</entry>
</feed>
