<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c, branch v5.9</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.9</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.9'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2020-07-14T18:38:41Z</updated>
<entry>
<title>drm/amdgpu: use ARRAY_SIZE() to add amdgpu debugfs files</title>
<updated>2020-07-14T18:38:41Z</updated>
<author>
<name>Xiaojie Yuan</name>
<email>xiaojie.yuan@amd.com</email>
</author>
<published>2020-07-13T05:55:42Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=9987d70d10eea0d685d4bfbf2101eaad64d36c37'/>
<id>urn:sha1:9987d70d10eea0d685d4bfbf2101eaad64d36c37</id>
<content type='text'>
to easily add new debugfs file w/o changing the hardcoded list count.

Signed-off-by: Xiaojie Yuan &lt;xiaojie.yuan@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>gpu/drm: Remove debug info about CPU address</title>
<updated>2020-07-08T13:04:21Z</updated>
<author>
<name>Tiezhu Yang</name>
<email>yangtiezhu@loongson.cn</email>
</author>
<published>2020-07-02T02:27:43Z</published>
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<id>urn:sha1:e241df6987023e341105696d71ead87fee1cc395</id>
<content type='text'>
When I update the latest kernel, I see the following "____ptrval____" boot
messages.

[    1.872600] radeon 0000:01:05.0: fence driver on ring 0 use gpu addr 0x0000000048000c00 and cpu addr 0x(____ptrval____)
[    1.879095] radeon 0000:01:05.0: fence driver on ring 5 use gpu addr 0x0000000040056038 and cpu addr 0x(____ptrval____)

Both radeon_fence_driver_start_ring() and amdgpu_fence_driver_start_ring()
have the similar issue, there exists the following two methods to solve it:
(1) Use "%pK" instead of "%p" so that the CPU address can be printed when
the kptr_restrict sysctl is set to 1.
(2) Just completely drop the CPU address suggested by Christian, because
the CPU address was useful in the past, but isn't any more. We now have a
debugfs file to read the current fence values.

Since the CPU address is not much useful, just remove the debug info about
CPU address.

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Tiezhu Yang &lt;yangtiezhu@loongson.cn&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: restrict the hw sched jobs number to power of two</title>
<updated>2020-07-01T05:59:23Z</updated>
<author>
<name>Kevin Wang</name>
<email>kevin1.wang@amd.com</email>
</author>
<published>2020-01-19T09:20:43Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=5d5bd5e32e6e12ab8d844b4b1a1235eb7f00c668'/>
<id>urn:sha1:5d5bd5e32e6e12ab8d844b4b1a1235eb7f00c668</id>
<content type='text'>
the module parameter sched_hw_submission is probably from user mode,
and the kernel need to check whether it is legal.

1. align hw sched jobs to power of 2 and set minimum number is 2.
2. use kernel api is_power_of_2() to simplify driver code.

Signed-off-by: Kevin Wang &lt;kevin1.wang@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/fence: fix ref count leak when pm_runtime_get_sync fails</title>
<updated>2020-07-01T05:59:22Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2020-06-17T18:50:02Z</published>
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<id>urn:sha1:e520d3e0d2818aafcdf9d8b60916754d8fedc366</id>
<content type='text'>
The call to pm_runtime_get_sync increments the counter even in case of
failure, leading to incorrect ref count.
In case of failure, decrement the ref count before returning.

Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Acked-by: Rajneesh Bhardwaj &lt;rajneesh.bhardwaj@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/fence: use the no_scheduler flag</title>
<updated>2020-07-01T05:59:16Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2020-06-02T18:51:36Z</published>
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<id>urn:sha1:730c2eb977a0b1cf950a94da1bec064f401fb8b0</id>
<content type='text'>
Rather than checking the ring type manually.  We already set
this for MES and KIQ (and a few other special cases).

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: skip GPU scheduler setup for KIQ and MES ring</title>
<updated>2020-07-01T05:59:13Z</updated>
<author>
<name>Likun Gao</name>
<email>Likun.Gao@amd.com</email>
</author>
<published>2020-04-15T03:33:15Z</published>
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<id>urn:sha1:514505014cb84ed463a25d9e6c519d34a683c284</id>
<content type='text'>
Fix the coding error to skip GPU scheduler setup for KIQ and MES ring.

Signed-off-by: Likun Gao &lt;Likun.Gao@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: no need to set up GPU scheduler for mes ring</title>
<updated>2020-07-01T05:59:08Z</updated>
<author>
<name>Jack Xiao</name>
<email>Jack.Xiao@amd.com</email>
</author>
<published>2019-10-21T05:49:38Z</published>
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<id>urn:sha1:03195e8063e26f556c6adbe6a9413b36f4b791eb</id>
<content type='text'>
As mes ring directly submits to hardwared,
it's no need to set up GPU scheduler for mes ring.

Signed-off-by: Jack Xiao &lt;Jack.Xiao@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: avoid dereferencing a NULL pointer</title>
<updated>2020-07-01T05:59:07Z</updated>
<author>
<name>Jack Xiao</name>
<email>Jack.Xiao@amd.com</email>
</author>
<published>2019-06-05T08:30:13Z</published>
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<id>urn:sha1:55611b507fd6453d26030c0c0619fdf0c262766d</id>
<content type='text'>
Check if irq_src is NULL to avoid dereferencing a NULL pointer,
for MES ring is uneccessary to recieve an interrupt notification.

Signed-off-by: Jack Xiao &lt;Jack.Xiao@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: protect ring overrun</title>
<updated>2020-04-24T15:42:11Z</updated>
<author>
<name>Yintian Tao</name>
<email>yttao@amd.com</email>
</author>
<published>2020-04-23T04:05:54Z</published>
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<id>urn:sha1:04e4e2e9558326316cf3e32d46cca83cc3861ef0</id>
<content type='text'>
Wait for the oldest sequence on the ring
to be signaled in order to make sure there
will be no command overrun.

v2: fix coding stype and remove abs operation
v3: remove the initialization of variable r

Signed-off-by: Yintian Tao &lt;yttao@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/fence: move debugfs init into core amdgpu debugfs</title>
<updated>2020-02-26T19:21:12Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2020-02-04T17:59:02Z</published>
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<id>urn:sha1:24038d581c751685bcbf25535ad8770b282d1cac</id>
<content type='text'>
In order to remove the load and unload drm callbacks,
we need to reorder the init sequence to move all the drm
debugfs file handling.  Do this for fence handling.

Tested-by: Thomas Zimmermann &lt;tzimmermann@suse.de&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
