<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c, branch v5.0</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.0</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.0'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2018-11-28T20:55:33Z</updated>
<entry>
<title>drm/amdgpu: Use asic specific doorbell index instead of macro definition</title>
<updated>2018-11-28T20:55:33Z</updated>
<author>
<name>Oak Zeng</name>
<email>ozeng@amd.com</email>
</author>
<published>2018-11-19T21:20:07Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=9564f1928ed29b093bb997df9573e8edae61983d'/>
<id>urn:sha1:9564f1928ed29b093bb997df9573e8edae61983d</id>
<content type='text'>
ASIC specific doorbell layout is used instead of enum definition

Signed-off-by: Oak Zeng &lt;ozeng@amd.com&gt;
Suggested-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Suggested-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: separate amdgpu_rlc into a single file</title>
<updated>2018-11-09T21:29:02Z</updated>
<author>
<name>Likun Gao</name>
<email>Likun.Gao@amd.com</email>
</author>
<published>2018-11-08T05:43:46Z</published>
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<id>urn:sha1:88dfc9a3dd47027c9ffc831635e5cf4e8ed3b781</id>
<content type='text'>
Separate the function and struct of RLC from the file of GFX.
Abstract the function of amdgpu_gfx_rlc_fini.

Signed-off-by: Likun Gao &lt;Likun.Gao@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Fix null point error</title>
<updated>2018-10-25T01:04:03Z</updated>
<author>
<name>Rex Zhu</name>
<email>Rex.Zhu@amd.com</email>
</author>
<published>2018-10-19T02:46:53Z</published>
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<id>urn:sha1:7179d24040d66de22e4710e943256be9e1045feb</id>
<content type='text'>
need to check adev-&gt;powerplay.pp_funcs first, becasue from
AI, the smu ip can be disabled by user, and the pp_handle
is null in this case.

Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Delay 100ms to enable gfx off feature</title>
<updated>2018-08-27T16:10:00Z</updated>
<author>
<name>Rex Zhu</name>
<email>Rex.Zhu@amd.com</email>
</author>
<published>2018-08-06T11:45:04Z</published>
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<id>urn:sha1:bf9b1d9dc7e99bb1395deb0ed0df3999ea527de3</id>
<content type='text'>
Original 500ms delay seems a bit large.
Change to 100 ms suggested by Christian.

Signed-off-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: move gfx definitions into amdgpu_gfx header</title>
<updated>2018-08-27T16:09:54Z</updated>
<author>
<name>Huang Rui</name>
<email>ray.huang@amd.com</email>
</author>
<published>2018-08-02T08:12:39Z</published>
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<id>urn:sha1:448fe1928ce415b8cae0425e5c7f066d6bd8b2de</id>
<content type='text'>
Demangle amdgpu.h

Signed-off-by: Huang Rui &lt;ray.huang@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Put enable gfx off feature to a delay thread</title>
<updated>2018-08-27T16:09:52Z</updated>
<author>
<name>Rex Zhu</name>
<email>Rex.Zhu@amd.com</email>
</author>
<published>2018-07-27T13:06:30Z</published>
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<id>urn:sha1:1e317b99f0c244bd8830918fdae9715210baf4fe</id>
<content type='text'>
delay to enable gfx off feature to avoid gfx on/off frequently
suggested by Alex and Evan.

Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add amdgpu_gfx_off_ctrl function</title>
<updated>2018-08-27T16:09:51Z</updated>
<author>
<name>Rex Zhu</name>
<email>Rex.Zhu@amd.com</email>
</author>
<published>2018-07-30T08:59:09Z</published>
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<id>urn:sha1:d23ee13fba23a3039971a976b2c4857cb5ba9c73</id>
<content type='text'>
v2:
   1. drop the special handling for the hw IP
      suggested by hawking and Christian.
   2. refine the variable name suggested by Flora.

This funciton as the entry of gfx off feature.
we arbitrat gfx off feature enable/disable in this
function.

Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: use queue 0 for kiq ring</title>
<updated>2018-01-30T04:14:30Z</updated>
<author>
<name>Huang Rui</name>
<email>ray.huang@amd.com</email>
</author>
<published>2017-12-15T01:33:21Z</published>
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<id>urn:sha1:59fd27cd2fd762b08a1f54de8bbe3b82aba06a13</id>
<content type='text'>
It must use queue id 0, because CGPG_IDLE/SAVE/LOAD/RUN only can be issued on
queue 0.

Signed-off-by: Huang Rui &lt;ray.huang@amd.com&gt;
Acked-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: rename amdgpu_wb_* functions</title>
<updated>2017-12-18T15:59:07Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2017-12-14T21:03:43Z</published>
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<id>urn:sha1:131b4b3686b701079e8fb82eb9384c8acdd3fc72</id>
<content type='text'>
add device for consistency.

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: busywait KIQ register accessing (v4)</title>
<updated>2017-10-19T19:27:19Z</updated>
<author>
<name>pding</name>
<email>Pixel.Ding@amd.com</email>
</author>
<published>2017-10-13T07:38:35Z</published>
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<id>urn:sha1:43ca8efa46d9b1c4defa1b27c4dd1ef3866aaad9</id>
<content type='text'>
Register accessing is performed when IRQ is disabled. Never sleep in
this function.

Known issue: dead sleep in many use cases of index/data registers.

v2:
 - wrap polling fence functions.
 - don't trigger IRQ for polling in case of wrongly fence signal.

v3:
 - handle wrap round gracefully.
 - add comments for polling function

v4:
 - don't return negative timeout confused with error code

Signed-off-by: pding &lt;Pixel.Ding@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
