<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c, branch v6.12</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v6.12</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v6.12'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2024-08-16T18:27:50Z</updated>
<entry>
<title>drm/amdgpu: abort KIQ waits when there is a pending reset</title>
<updated>2024-08-16T18:27:50Z</updated>
<author>
<name>Victor Skvortsov</name>
<email>victor.skvortsov@amd.com</email>
</author>
<published>2024-08-02T18:22:26Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=19cff16559a4f2d763faf4f8392bf86d3a21b93c'/>
<id>urn:sha1:19cff16559a4f2d763faf4f8392bf86d3a21b93c</id>
<content type='text'>
Stop waiting for the KIQ to return back when there is a reset pending.
It's quite likely that the KIQ will never response.

Signed-off-by: Koenig Christian &lt;Christian.Koenig@amd.com&gt;
Suggested-by: Lazar Lijo &lt;Lijo.Lazar@amd.com&gt;
Tested-by: Victor Skvortsov &lt;victor.skvortsov@amd.com&gt;
Signed-off-by: Victor Skvortsov &lt;victor.skvortsov@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/mes: add multiple mes ring instances support</title>
<updated>2024-08-13T14:29:25Z</updated>
<author>
<name>Jack Xiao</name>
<email>Jack.Xiao@amd.com</email>
</author>
<published>2024-08-07T03:53:35Z</published>
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<id>urn:sha1:c7d4355648ffa02a1551495b05c71ea6c884d29c</id>
<content type='text'>
Add multiple mes ring instances in mes structure to support
multiple mes pipes.

Signed-off-by: Jack Xiao &lt;Jack.Xiao@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add tmz support for GC IP v11.5.2</title>
<updated>2024-07-02T22:05:09Z</updated>
<author>
<name>Tim Huang</name>
<email>Tim.Huang@amd.com</email>
</author>
<published>2024-05-14T06:14:17Z</published>
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<id>urn:sha1:98392782df666cee2b9d4161494bb23177d67605</id>
<content type='text'>
Add tmz support for GC 11.5.2.

Signed-off-by: Tim Huang &lt;Tim.Huang@amd.com&gt;
Reviewed-by: Yifan Zhang &lt;yifan1.zhang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add missing error handling in function amdgpu_gmc_flush_gpu_tlb_pasid</title>
<updated>2024-06-27T21:10:39Z</updated>
<author>
<name>Bob Zhou</name>
<email>bob.zhou@amd.com</email>
</author>
<published>2024-06-20T07:40:06Z</published>
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<id>urn:sha1:9ff2e14cf013fa887e269bdc5ea3cffacada8635</id>
<content type='text'>
Fix the unchecked return value warning reported by Coverity,
so add error handling.

Signed-off-by: Bob Zhou &lt;bob.zhou@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fix locking scope when flushing tlb</title>
<updated>2024-06-14T20:15:59Z</updated>
<author>
<name>Yunxiang Li</name>
<email>Yunxiang.Li@amd.com</email>
</author>
<published>2024-05-23T11:48:19Z</published>
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<id>urn:sha1:9c33e5fd4fb63b793d9a92bf35d190630d9bada4</id>
<content type='text'>
Which method is used to flush tlb does not depend on whether a reset is
in progress or not. We should skip flush altogether if the GPU will get
reset. So put both path under reset_domain read lock.

Signed-off-by: Yunxiang Li &lt;Yunxiang.Li@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
CC: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu: call flush_gpu_tlb directly in gfxhub enable</title>
<updated>2024-06-14T20:15:59Z</updated>
<author>
<name>Yunxiang Li</name>
<email>Yunxiang.Li@amd.com</email>
</author>
<published>2024-06-04T16:56:56Z</published>
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<id>urn:sha1:ba531117a87d55f607f865b89eb83665e8e99b83</id>
<content type='text'>
Here since we are in reset and takes the reset_domain write side lock
already. We can't use the flush tlb helper which tries to take the read
side.

Signed-off-by: Yunxiang Li &lt;Yunxiang.Li@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Remove GC HW IP 9.3.0 from noretry=1</title>
<updated>2024-05-17T21:40:38Z</updated>
<author>
<name>Tim Van Patten</name>
<email>timvp@google.com</email>
</author>
<published>2024-05-16T17:57:25Z</published>
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<id>urn:sha1:1446226d32a45bb7c4f63195a59be8c08defe658</id>
<content type='text'>
The following commit updated gmc-&gt;noretry from 0 to 1 for GC HW IP
9.3.0:

    commit 5f3854f1f4e2 ("drm/amdgpu: add more cases to noretry=1")

This causes the device to hang when a page fault occurs, until the
device is rebooted. Instead, revert back to gmc-&gt;noretry=0 so the device
is still responsive.

Fixes: 5f3854f1f4e2 ("drm/amdgpu: add more cases to noretry=1")
Signed-off-by: Tim Van Patten &lt;timvp@google.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Use NPS ranges from discovery table</title>
<updated>2024-05-17T21:40:36Z</updated>
<author>
<name>Lijo Lazar</name>
<email>lijo.lazar@amd.com</email>
</author>
<published>2024-05-09T11:32:33Z</published>
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<id>urn:sha1:b194d21b9bcc15b50df1bc3ff7428e51c2918a6f</id>
<content type='text'>
Add GMC API to fetch NPS range information from discovery table. Use NPS
range information in GMC 9.4.3 SOCs when available, otherwise fallback
to software method.

Signed-off-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Le Ma &lt;le.ma@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: remove structurally dead code for amd_gmc</title>
<updated>2024-05-13T20:11:53Z</updated>
<author>
<name>Jesse Zhang</name>
<email>jesse.zhang@amd.com</email>
</author>
<published>2024-05-08T10:17:43Z</published>
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<id>urn:sha1:e2bff63ba6f875cb879c90758662f193f040d033</id>
<content type='text'>
This code cannot be reached: return sysfs_emit(buf, "UNK....)

Signed-off-by: Jesse Zhang &lt;Jesse.Zhang@amd.com&gt;
Reviewed-by: Tim Huang &lt;Tim.Huang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add gfx v9_4_4 ip block</title>
<updated>2024-05-02T19:49:16Z</updated>
<author>
<name>Hawking Zhang</name>
<email>Hawking.Zhang@amd.com</email>
</author>
<published>2024-04-16T21:32:46Z</published>
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<id>urn:sha1:5f571c61b90f905e881c3bd591de65d9d0e1722c</id>
<content type='text'>
Add gfx v9_4_4 ip block support

Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Le Ma &lt;le.ma@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
