<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c, branch v6.16</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v6.16</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v6.16'/>
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<updated>2025-04-30T22:03:02Z</updated>
<entry>
<title>drm/amdgpu: Disallow partition query during reset</title>
<updated>2025-04-30T22:03:02Z</updated>
<author>
<name>Lijo Lazar</name>
<email>lijo.lazar@amd.com</email>
</author>
<published>2025-04-16T06:53:44Z</published>
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<id>urn:sha1:75f138db48c5c493f0ac198c2579d52fc6a4c4a0</id>
<content type='text'>
Reject queries to get current partition modes during reset. Also, don't
accept sysfs interface requests to switch compute partition mode while
in reset.

Signed-off-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Asad Kamal &lt;asad.kamal@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Increase KIQ invalidate_tlbs timeout</title>
<updated>2025-04-07T19:18:30Z</updated>
<author>
<name>Jay Cornwall</name>
<email>jay.cornwall@amd.com</email>
</author>
<published>2025-03-21T18:19:05Z</published>
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<id>urn:sha1:3666ed821832f42baaf25f362680dda603cde732</id>
<content type='text'>
KIQ invalidate_tlbs request has been seen to marginally exceed the
configured 100 ms timeout on systems under load.

All other KIQ requests in the driver use a 10 second timeout. Use a
similar timeout implementation on the invalidate_tlbs path.

v2: Poll once before msleep
v3: Fix return value

Signed-off-by: Jay Cornwall &lt;jay.cornwall@amd.com&gt;
Cc: Kent Russell &lt;kent.russell@amd.com&gt;
Reviewed-by: Harish Kasiviswanathan &lt;Harish.Kasiviswanathan@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Optimize VM invalidation engine allocation and synchronize GPU TLB flush</title>
<updated>2025-03-21T16:16:35Z</updated>
<author>
<name>Jesse.zhang@amd.com</name>
<email>Jesse.zhang@amd.com</email>
</author>
<published>2025-02-25T07:25:00Z</published>
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<id>urn:sha1:b09cdeb4d38872b84c6d59878915eae2adbe9d2b</id>
<content type='text'>
- Modify the VM invalidation engine allocation logic to handle SDMA page rings.
  SDMA page rings now share the VM invalidation engine with SDMA gfx rings instead of
  allocating a separate engine. This change ensures efficient resource management and
  avoids the issue of insufficient VM invalidation engines.

- Add synchronization for GPU TLB flush operations in gmc_v9_0.c.
  Use spin_lock and spin_unlock to ensure thread safety and prevent race conditions
  during TLB flush operations. This improves the stability and reliability of the driver,
  especially in multi-threaded environments.

 v2: replace the sdma ring check with a function `amdgpu_sdma_is_page_queue`
 to check if a ring is an SDMA page queue.(Lijo)

 v3: Add GC version check, only enabled on GC9.4.3/9.4.4/9.5.0
 v4: Fix code style and add more detailed description (Christian)
 v5: Remove dependency on vm_inv_eng loop order, explicitly lookup shared inv_eng(Christian/Lijo)
 v6: Added search shared ring function amdgpu_sdma_get_shared_ring (Lijo)

Suggested-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Jesse Zhang &lt;jesse.zhang@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fix spelling typos</title>
<updated>2025-03-05T15:37:13Z</updated>
<author>
<name>Alexandre Demers</name>
<email>alexandre.f.demers@gmail.com</email>
</author>
<published>2025-02-27T05:05:04Z</published>
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<id>urn:sha1:ce43abd7ec9464cf954f90e1c69e11768b02fa0a</id>
<content type='text'>
Found some typos while exploring amdgpu code.

Signed-off-by: Alexandre Demers &lt;alexandre.f.demers@gmail.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add RAS CPER ring buffer</title>
<updated>2025-02-17T19:09:29Z</updated>
<author>
<name>Tao Zhou</name>
<email>tao.zhou1@amd.com</email>
</author>
<published>2025-01-22T08:55:51Z</published>
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<id>urn:sha1:4d614ce8ffd757e4c7944bf9b5598b4a250a8a61</id>
<content type='text'>
And initialize it, this is a pure software ring to store RAS CPER data.

v2: change ring size to 0x100000
v2: update the initialization of count_dw of cper ring, it's dword
variable
v3: skip VM inv eng for cper
v3: init/fini when aca enabled

Signed-off-by: Tao Zhou &lt;tao.zhou1@amd.com&gt;
Signed-off-by: Xiang Liu &lt;xiang.liu@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Set noretry default for GC 9.5.0</title>
<updated>2025-02-13T02:02:56Z</updated>
<author>
<name>Amber Lin</name>
<email>Amber.Lin@amd.com</email>
</author>
<published>2025-01-06T15:56:29Z</published>
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<id>urn:sha1:46d0436a3e401692a614455861a82a0c852a6fd1</id>
<content type='text'>
Set GC 9.5.0 noretry default as 1 for better performance. It can be
changed by the administrator using amdgpu.noretry=0 or by the user using
HSA_XNACK=1 environment variable.

Signed-off-by: Amber Lin &lt;Amber.Lin@amd.com&gt;
Reviewed-by: Harish Kasiviswanathan &lt;Harish.Kasiviwanathan@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add support for GC IP version 11.5.3</title>
<updated>2025-02-13T02:02:55Z</updated>
<author>
<name>Tim Huang</name>
<email>tim.huang@amd.com</email>
</author>
<published>2024-12-05T08:24:44Z</published>
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<id>urn:sha1:b784faeba229ad1b2cb0f9c0dbddc48411a3bc8c</id>
<content type='text'>
This initializes GC IP version 11.5.3.

Signed-off-by: Tim Huang &lt;tim.huang@amd.com&gt;
Reviewed-by: Yifan Zhang &lt;yifan1.zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Fix off by one in current_memory_partition_show()</title>
<updated>2024-10-15T15:26:35Z</updated>
<author>
<name>Dan Carpenter</name>
<email>dan.carpenter@linaro.org</email>
</author>
<published>2024-10-10T18:35:36Z</published>
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<id>urn:sha1:9f7e94af35996effead76ff2837b5ba322e38963</id>
<content type='text'>
The &gt;= ARRAY_SIZE() should be &gt; ARRAY_SIZE() to prevent an out of
bounds read.

Fixes: 012be6f22c01 ("drm/amdgpu: Add sysfs interfaces for NPS mode")
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Dan Carpenter &lt;dan.carpenter@linaro.org&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Fetch NPS mode for GCv9.4.3 VFs</title>
<updated>2024-10-15T15:19:46Z</updated>
<author>
<name>Lijo Lazar</name>
<email>lijo.lazar@amd.com</email>
</author>
<published>2024-09-13T11:47:19Z</published>
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<id>urn:sha1:b3c687169256ec637172b661cf59518eb756db28</id>
<content type='text'>
Use the memory ranges published in discovery table to deduce NPS mode
of GC v9.4.3 VFs.

Signed-off-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Vignesh Chander &lt;Vignesh.Chander@amd.com&gt;
Tested-by: Vignesh Chander &lt;Vignesh.Chander@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Check gmc requirement for reset on init</title>
<updated>2024-10-15T15:16:32Z</updated>
<author>
<name>Lijo Lazar</name>
<email>lijo.lazar@amd.com</email>
</author>
<published>2024-09-20T08:47:30Z</published>
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<id>urn:sha1:ed3dac4bf9588b5a68e1a85ac45cbbe180df6d4b</id>
<content type='text'>
Add a callback to check if there is any condition detected by GMC block
for reset on init. One case is if a pending NPS change request is
detected. If reset is done because of NPS switch, refresh NPS info from
discovery table.

Signed-off-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Feifei Xu &lt;Feifei.Xu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
