<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c, branch v6.17</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v6.17</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v6.17'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2025-06-24T14:04:16Z</updated>
<entry>
<title>drm/amdgpu: Convert init_mem_ranges into common helpers</title>
<updated>2025-06-24T14:04:16Z</updated>
<author>
<name>Hawking Zhang</name>
<email>Hawking.Zhang@amd.com</email>
</author>
<published>2025-06-21T13:27:22Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=5562b669928af29d44cc0471632641f7b88c6c88'/>
<id>urn:sha1:5562b669928af29d44cc0471632641f7b88c6c88</id>
<content type='text'>
They can be shared across multiple products

Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Convert query_memory_partition into common helpers</title>
<updated>2025-06-24T14:04:09Z</updated>
<author>
<name>Hawking Zhang</name>
<email>Hawking.Zhang@amd.com</email>
</author>
<published>2025-06-21T13:11:30Z</published>
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<id>urn:sha1:c9df2dcf9054273c7f493b7912744de6eefd2aea</id>
<content type='text'>
The query_memory_partition does not need to remain
as soc specific callbacks. They can be shared across
multiple products

Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: enable pdb0 for hibernation on SRIOV</title>
<updated>2025-06-18T16:19:15Z</updated>
<author>
<name>Samuel Zhang</name>
<email>guoqing.zhang@amd.com</email>
</author>
<published>2025-04-11T08:19:09Z</published>
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<id>urn:sha1:2f405eb45c5523aadf6faea1ca465cf3e6ad7866</id>
<content type='text'>
When switching to new GPU index after hibernation and then resume,
VRAM offset of each VRAM BO will be changed, and the cached gpu
addresses needed to updated.

This is to enable pdb0 and switch to use pdb0-based virtual gpu
address by default in amdgpu_bo_create_reserved(). since the virtual
addresses do not change, this can avoid the need to update all
cached gpu addresses all over the codebase.

Signed-off-by: Emily Deng &lt;Emily.Deng@amd.com&gt;
Signed-off-by: Samuel Zhang &lt;guoqing.zhang@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Disallow partition query during reset</title>
<updated>2025-04-30T22:03:02Z</updated>
<author>
<name>Lijo Lazar</name>
<email>lijo.lazar@amd.com</email>
</author>
<published>2025-04-16T06:53:44Z</published>
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<id>urn:sha1:75f138db48c5c493f0ac198c2579d52fc6a4c4a0</id>
<content type='text'>
Reject queries to get current partition modes during reset. Also, don't
accept sysfs interface requests to switch compute partition mode while
in reset.

Signed-off-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Asad Kamal &lt;asad.kamal@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Increase KIQ invalidate_tlbs timeout</title>
<updated>2025-04-07T19:18:30Z</updated>
<author>
<name>Jay Cornwall</name>
<email>jay.cornwall@amd.com</email>
</author>
<published>2025-03-21T18:19:05Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=3666ed821832f42baaf25f362680dda603cde732'/>
<id>urn:sha1:3666ed821832f42baaf25f362680dda603cde732</id>
<content type='text'>
KIQ invalidate_tlbs request has been seen to marginally exceed the
configured 100 ms timeout on systems under load.

All other KIQ requests in the driver use a 10 second timeout. Use a
similar timeout implementation on the invalidate_tlbs path.

v2: Poll once before msleep
v3: Fix return value

Signed-off-by: Jay Cornwall &lt;jay.cornwall@amd.com&gt;
Cc: Kent Russell &lt;kent.russell@amd.com&gt;
Reviewed-by: Harish Kasiviswanathan &lt;Harish.Kasiviswanathan@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Optimize VM invalidation engine allocation and synchronize GPU TLB flush</title>
<updated>2025-03-21T16:16:35Z</updated>
<author>
<name>Jesse.zhang@amd.com</name>
<email>Jesse.zhang@amd.com</email>
</author>
<published>2025-02-25T07:25:00Z</published>
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<id>urn:sha1:b09cdeb4d38872b84c6d59878915eae2adbe9d2b</id>
<content type='text'>
- Modify the VM invalidation engine allocation logic to handle SDMA page rings.
  SDMA page rings now share the VM invalidation engine with SDMA gfx rings instead of
  allocating a separate engine. This change ensures efficient resource management and
  avoids the issue of insufficient VM invalidation engines.

- Add synchronization for GPU TLB flush operations in gmc_v9_0.c.
  Use spin_lock and spin_unlock to ensure thread safety and prevent race conditions
  during TLB flush operations. This improves the stability and reliability of the driver,
  especially in multi-threaded environments.

 v2: replace the sdma ring check with a function `amdgpu_sdma_is_page_queue`
 to check if a ring is an SDMA page queue.(Lijo)

 v3: Add GC version check, only enabled on GC9.4.3/9.4.4/9.5.0
 v4: Fix code style and add more detailed description (Christian)
 v5: Remove dependency on vm_inv_eng loop order, explicitly lookup shared inv_eng(Christian/Lijo)
 v6: Added search shared ring function amdgpu_sdma_get_shared_ring (Lijo)

Suggested-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Jesse Zhang &lt;jesse.zhang@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fix spelling typos</title>
<updated>2025-03-05T15:37:13Z</updated>
<author>
<name>Alexandre Demers</name>
<email>alexandre.f.demers@gmail.com</email>
</author>
<published>2025-02-27T05:05:04Z</published>
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<id>urn:sha1:ce43abd7ec9464cf954f90e1c69e11768b02fa0a</id>
<content type='text'>
Found some typos while exploring amdgpu code.

Signed-off-by: Alexandre Demers &lt;alexandre.f.demers@gmail.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add RAS CPER ring buffer</title>
<updated>2025-02-17T19:09:29Z</updated>
<author>
<name>Tao Zhou</name>
<email>tao.zhou1@amd.com</email>
</author>
<published>2025-01-22T08:55:51Z</published>
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<id>urn:sha1:4d614ce8ffd757e4c7944bf9b5598b4a250a8a61</id>
<content type='text'>
And initialize it, this is a pure software ring to store RAS CPER data.

v2: change ring size to 0x100000
v2: update the initialization of count_dw of cper ring, it's dword
variable
v3: skip VM inv eng for cper
v3: init/fini when aca enabled

Signed-off-by: Tao Zhou &lt;tao.zhou1@amd.com&gt;
Signed-off-by: Xiang Liu &lt;xiang.liu@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Set noretry default for GC 9.5.0</title>
<updated>2025-02-13T02:02:56Z</updated>
<author>
<name>Amber Lin</name>
<email>Amber.Lin@amd.com</email>
</author>
<published>2025-01-06T15:56:29Z</published>
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<id>urn:sha1:46d0436a3e401692a614455861a82a0c852a6fd1</id>
<content type='text'>
Set GC 9.5.0 noretry default as 1 for better performance. It can be
changed by the administrator using amdgpu.noretry=0 or by the user using
HSA_XNACK=1 environment variable.

Signed-off-by: Amber Lin &lt;Amber.Lin@amd.com&gt;
Reviewed-by: Harish Kasiviswanathan &lt;Harish.Kasiviwanathan@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add support for GC IP version 11.5.3</title>
<updated>2025-02-13T02:02:55Z</updated>
<author>
<name>Tim Huang</name>
<email>tim.huang@amd.com</email>
</author>
<published>2024-12-05T08:24:44Z</published>
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<id>urn:sha1:b784faeba229ad1b2cb0f9c0dbddc48411a3bc8c</id>
<content type='text'>
This initializes GC IP version 11.5.3.

Signed-off-by: Tim Huang &lt;tim.huang@amd.com&gt;
Reviewed-by: Yifan Zhang &lt;yifan1.zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
