<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h, branch v5.8</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.8</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.8'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2020-04-28T20:20:29Z</updated>
<entry>
<title>drm/amdgpu: implement TMZ accessor (v3)</title>
<updated>2020-04-28T20:20:29Z</updated>
<author>
<name>Luben Tuikov</name>
<email>luben.tuikov@amd.com</email>
</author>
<published>2020-03-19T20:47:51Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=c6252390fccdd768d1250a45cbd2a7e3610a1283'/>
<id>urn:sha1:c6252390fccdd768d1250a45cbd2a7e3610a1283</id>
<content type='text'>
Implement an accessor of adev-&gt;tmz.enabled. Let not
code around access it as "if (adev-&gt;tmz.enabled)"
as the organization may change. Instead...

Recruit "bool amdgpu_is_tmz(adev)" to return
exactly this Boolean value. That is, this function
is now an accessor of an already initialized and
set adev and adev-&gt;tmz.

Add "void amdgpu_gmc_tmz_set(adev)" to check and
set adev-&gt;gmc.tmz_enabled at initialization
time. After which one uses "bool
amdgpu_is_tmz(adev)" to query whether adev
supports TMZ.

Also, remove circular header file include.

v2: Remove amdgpu_tmz.[ch] as requested.
v3: Move TMZ into GMC.

Signed-off-by: Luben Tuikov &lt;luben.tuikov@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>amdgpu/gmc_v9: save/restore sdpif regs during S3</title>
<updated>2020-02-25T16:01:26Z</updated>
<author>
<name>Shirish S</name>
<email>shirish.s@amd.com</email>
</author>
<published>2020-01-27T11:05:24Z</published>
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<id>urn:sha1:c2ecd79bec4ecc7f4fa52d91ea9bd3d69e3f54d5</id>
<content type='text'>
fixes S3 issue with IOMMU + S/G  enabled @ 64M VRAM.

Suggested-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Shirish S &lt;shirish.s@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>Revert "drm/amdgpu: fix modprobe failure of the secondary GPU when GDDR6 training enabled(V5)"</title>
<updated>2020-01-22T21:55:27Z</updated>
<author>
<name>Tianci.Yin</name>
<email>tianci.yin@amd.com</email>
</author>
<published>2020-01-20T09:20:10Z</published>
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<id>urn:sha1:7db1d560a4fab1e4668b1964e77f52cefce9e9c7</id>
<content type='text'>
This reverts commit 9e441478623fd913d4340654682b19f0c24e629d.

The patch will be replaced with a better solution, revert it.

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Tianci.Yin &lt;tianci.yin@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fix modprobe failure of the secondary GPU when GDDR6 training enabled(V5)</title>
<updated>2020-01-16T18:35:37Z</updated>
<author>
<name>Tianci.Yin</name>
<email>tianci.yin@amd.com</email>
</author>
<published>2020-01-09T07:38:39Z</published>
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<id>urn:sha1:9e441478623fd913d4340654682b19f0c24e629d</id>
<content type='text'>
[why]
In dual GPUs scenario, stolen_size is assigned to zero on the secondary GPU,
since there is no pre-OS console using that memory. Then the bottom region of
VRAM was allocated as GTT, unfortunately a small region of bottom VRAM was
encroached by UMC firmware during GDDR6 BIST training, this cause page fault.

[how]
Forcing stolen_size to 3MB, then the bottom region of VRAM was
allocated as stolen memory, GTT corruption avoid.

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Feifei Xu &lt;Feifei.Xu@amd.com&gt;
Signed-off-by: Tianci.Yin &lt;tianci.yin@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: export function to flush TLB via pasid</title>
<updated>2020-01-16T18:34:27Z</updated>
<author>
<name>Alex Sierra</name>
<email>alex.sierra@amd.com</email>
</author>
<published>2019-12-20T05:40:19Z</published>
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<id>urn:sha1:ea930000a6dcd161346c957545f7e67b3f77ec06</id>
<content type='text'>
This can be used directly from amdgpu and amdkfd to invalidate
TLB through pasid.
It supports gmc v7, v8, v9 and v10.

Signed-off-by: Alex Sierra &lt;alex.sierra@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/gmc: move invaliation bitmap setup to common code</title>
<updated>2020-01-07T17:03:42Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2020-01-06T18:14:27Z</published>
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<id>urn:sha1:bdbe90f04d24ba9f9bc8b5fa8aa0269473f92509</id>
<content type='text'>
So it can be shared with newer GMC versions.

Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: initialize vm_inv_eng0_sem for gfxhub and mmhub</title>
<updated>2019-11-22T19:55:19Z</updated>
<author>
<name>changzhu</name>
<email>Changfeng.Zhu@amd.com</email>
</author>
<published>2019-11-19T02:18:39Z</published>
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<id>urn:sha1:6c2c8972374ac5c35078d36d7559f64c368f7b33</id>
<content type='text'>
SW must acquire/release one of the vm_invalidate_eng*_sem around the
invalidation req/ack. Through this way,it can avoid losing invalidate
acknowledge state across power-gating off cycle.
To use vm_invalidate_eng*_sem, it needs to initialize
vm_invalidate_eng*_sem firstly.

Signed-off-by: changzhu &lt;Changfeng.Zhu@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu: Add comments to gmc structure</title>
<updated>2019-11-07T23:08:07Z</updated>
<author>
<name>Oak Zeng</name>
<email>Oak.Zeng@amd.com</email>
</author>
<published>2019-11-06T17:18:54Z</published>
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<id>urn:sha1:f6baa07497fbebcc05096097dfd9f32b8caa50b1</id>
<content type='text'>
Explain fields like aper_base, agp_start etc. The definition
of those fields are confusing as they are from different view
(CPU or GPU). Add comments for easier understand.

Signed-off-by: Oak Zeng &lt;Oak.Zeng@amd.com&gt;
Reviewed-by: Alex Deucher &lt;Alex.Deucher@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Report vram vendor with sysfs (v3)</title>
<updated>2019-10-07T20:11:07Z</updated>
<author>
<name>Ori Messinger</name>
<email>Ori.Messinger@amd.com</email>
</author>
<published>2019-10-02T14:02:07Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=ad02e08e05781c3dabe7853f39cffb69169e96b2'/>
<id>urn:sha1:ad02e08e05781c3dabe7853f39cffb69169e96b2</id>
<content type='text'>
The vram vendor can be found as a separate sysfs file at:
/sys/class/drm/card[X]/device/mem_info_vram_vendor
The vram vendor is displayed as a string value.

v2: Use correct bit masking, and cache vram_vendor in gmc
v3: Drop unused functions for vram width, type, and vendor

Signed-off-by: Ori Messinger &lt;ori.messinger@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: implement common gmc_ras_late_init</title>
<updated>2019-10-03T14:11:03Z</updated>
<author>
<name>Tao Zhou</name>
<email>tao.zhou1@amd.com</email>
</author>
<published>2019-09-18T10:31:07Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=ba0834921400613839b28b572fdb713281b473d9'/>
<id>urn:sha1:ba0834921400613839b28b572fdb713281b473d9</id>
<content type='text'>
common gmc_ecc_late_init can be shared among all generations of gmc

v2: rename gmc_ecc_late_init to gmc_ras_late_init

Signed-off-by: Tao Zhou &lt;tao.zhou1@amd.com&gt;
Reviewed-by: Guchun Chen &lt;guchun.chen@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
