<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h, branch v6.17</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v6.17</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v6.17'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2025-06-24T14:04:16Z</updated>
<entry>
<title>drm/amdgpu: Convert init_mem_ranges into common helpers</title>
<updated>2025-06-24T14:04:16Z</updated>
<author>
<name>Hawking Zhang</name>
<email>Hawking.Zhang@amd.com</email>
</author>
<published>2025-06-21T13:27:22Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=5562b669928af29d44cc0471632641f7b88c6c88'/>
<id>urn:sha1:5562b669928af29d44cc0471632641f7b88c6c88</id>
<content type='text'>
They can be shared across multiple products

Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Convert query_memory_partition into common helpers</title>
<updated>2025-06-24T14:04:09Z</updated>
<author>
<name>Hawking Zhang</name>
<email>Hawking.Zhang@amd.com</email>
</author>
<published>2025-06-21T13:11:30Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=c9df2dcf9054273c7f493b7912744de6eefd2aea'/>
<id>urn:sha1:c9df2dcf9054273c7f493b7912744de6eefd2aea</id>
<content type='text'>
The query_memory_partition does not need to remain
as soc specific callbacks. They can be shared across
multiple products

Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Move MAX_MEM_RANGES to amdgpu_gmc.h</title>
<updated>2025-06-24T14:04:06Z</updated>
<author>
<name>Hawking Zhang</name>
<email>Hawking.Zhang@amd.com</email>
</author>
<published>2025-06-13T11:58:49Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=97c894758b9f1d7a01794d85b95a7b2854d85009'/>
<id>urn:sha1:97c894758b9f1d7a01794d85b95a7b2854d85009</id>
<content type='text'>
This relocation allows MAX_MEM_RANGES to be shared
across multiple products

Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: enable pdb0 for hibernation on SRIOV</title>
<updated>2025-06-18T16:19:15Z</updated>
<author>
<name>Samuel Zhang</name>
<email>guoqing.zhang@amd.com</email>
</author>
<published>2025-04-11T08:19:09Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=2f405eb45c5523aadf6faea1ca465cf3e6ad7866'/>
<id>urn:sha1:2f405eb45c5523aadf6faea1ca465cf3e6ad7866</id>
<content type='text'>
When switching to new GPU index after hibernation and then resume,
VRAM offset of each VRAM BO will be changed, and the cached gpu
addresses needed to updated.

This is to enable pdb0 and switch to use pdb0-based virtual gpu
address by default in amdgpu_bo_create_reserved(). since the virtual
addresses do not change, this can avoid the need to update all
cached gpu addresses all over the codebase.

Signed-off-by: Emily Deng &lt;Emily.Deng@amd.com&gt;
Signed-off-by: Samuel Zhang &lt;guoqing.zhang@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdkfd: Support chain runlists of XNACK+/XNACK-</title>
<updated>2025-05-16T17:37:29Z</updated>
<author>
<name>Amber Lin</name>
<email>Amber.Lin@amd.com</email>
</author>
<published>2025-04-29T20:11:55Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=e3d0870a90a8e3f63c486438ac6a77ab828f8d8d'/>
<id>urn:sha1:e3d0870a90a8e3f63c486438ac6a77ab828f8d8d</id>
<content type='text'>
If the MEC firmware supports chaining runlists of XNACK+/XNACK-
processes, set SQ_CONFIG1 chicken bit and SET_RESOURCES bit 28.

When the MEC/HWS supports it, KFD checks the XNACK+/XNACK- processes mix
happens or not. If it does, enter over-subscription.

Signed-off-by: Amber Lin &lt;Amber.Lin@amd.com&gt;
Reviewed-by: Philip Yang &lt;Philip.Yang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Move xgmi definitions to xgmi header</title>
<updated>2025-02-27T21:50:04Z</updated>
<author>
<name>Lijo Lazar</name>
<email>lijo.lazar@amd.com</email>
</author>
<published>2025-02-06T10:46:43Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=6f16d101dab5ec6e8fc9567769f73ae8baa3fe38'/>
<id>urn:sha1:6f16d101dab5ec6e8fc9567769f73ae8baa3fe38</id>
<content type='text'>
Move definitions related to xgmi to amdgpu_xgmi header

Signed-off-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Fetch NPS mode for GCv9.4.3 VFs</title>
<updated>2024-10-15T15:19:46Z</updated>
<author>
<name>Lijo Lazar</name>
<email>lijo.lazar@amd.com</email>
</author>
<published>2024-09-13T11:47:19Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=b3c687169256ec637172b661cf59518eb756db28'/>
<id>urn:sha1:b3c687169256ec637172b661cf59518eb756db28</id>
<content type='text'>
Use the memory ranges published in discovery table to deduce NPS mode
of GC v9.4.3 VFs.

Signed-off-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Vignesh Chander &lt;Vignesh.Chander@amd.com&gt;
Tested-by: Vignesh Chander &lt;Vignesh.Chander@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Check gmc requirement for reset on init</title>
<updated>2024-10-15T15:16:32Z</updated>
<author>
<name>Lijo Lazar</name>
<email>lijo.lazar@amd.com</email>
</author>
<published>2024-09-20T08:47:30Z</published>
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<id>urn:sha1:ed3dac4bf9588b5a68e1a85ac45cbbe180df6d4b</id>
<content type='text'>
Add a callback to check if there is any condition detected by GMC block
for reset on init. One case is if a pending NPS change request is
detected. If reset is done because of NPS switch, refresh NPS info from
discovery table.

Signed-off-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Feifei Xu &lt;Feifei.Xu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Place NPS mode request on unload</title>
<updated>2024-10-15T15:16:20Z</updated>
<author>
<name>Lijo Lazar</name>
<email>lijo.lazar@amd.com</email>
</author>
<published>2024-09-20T07:44:40Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=ee52489d1210dbb894fda71957e1e9832126efda'/>
<id>urn:sha1:ee52489d1210dbb894fda71957e1e9832126efda</id>
<content type='text'>
If a user has requested NPS mode switch, place the request through PSP
during unload of the driver. For devices which are part of a hive, all
requests are placed together. If one of them fails, revert back to the
current NPS mode.

Signed-off-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Rajneesh Bhardwaj &lt;rajneesh.bhardwaj@amd.com&gt;
Reviewed-by: Feifei Xu &lt;Feifei.Xu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add sysfs interfaces for NPS mode</title>
<updated>2024-10-07T18:32:23Z</updated>
<author>
<name>Lijo Lazar</name>
<email>lijo.lazar@amd.com</email>
</author>
<published>2024-09-19T14:06:19Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=012be6f22c01e25c995c30f1f178ac11820dfb65'/>
<id>urn:sha1:012be6f22c01e25c995c30f1f178ac11820dfb65</id>
<content type='text'>
Add a sysfs interface to see available NPS modes to switch to -

	cat /sys/bus/pci/devices/../available_memory_paritition

Make the current_memory_partition sysfs node read/write for requesting a
new NPS mode. The request is only cached and at a later point a driver
unload/reload is required to switch to the new NPS mode.

Ex:
	echo NPS1 &gt; /sys/bus/pci/devices/../current_memory_paritition
	echo NPS4 &gt; /sys/bus/pci/devices/../current_memory_paritition

The above interfaces will be available only if the SOC supports more than
one NPS mode.

Also modify the current memory partition sysfs logic to be more
generic.

Signed-off-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Rajneesh Bhardwaj &lt;rajneesh.bhardwaj@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
