<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c, branch v4.19</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v4.19</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v4.19'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2018-08-22T21:05:20Z</updated>
<entry>
<title>amdgpu: fix multi-process hang issue</title>
<updated>2018-08-22T21:05:20Z</updated>
<author>
<name>Emily Deng</name>
<email>Emily.Deng@amd.com</email>
</author>
<published>2018-08-22T12:18:25Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=2f40c6eac74a2a60921cdec9e9a8a57e88e31434'/>
<id>urn:sha1:2f40c6eac74a2a60921cdec9e9a8a57e88e31434</id>
<content type='text'>
SWDEV-146499: hang during multi vulkan process testing

cause:
the second frame's PREAMBLE_IB have clear-state
and LOAD actions, those actions ruin the pipeline
that is still doing process in the previous frame's
work-load IB.

fix:
need insert pipeline sync if have context switch for
SRIOV (because only SRIOV will report PREEMPTION flag
to UMD)

Signed-off-by: Monk Liu &lt;Monk.Liu@amd.com&gt;
Signed-off-by: Emily Deng &lt;Emily.Deng@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: remove fence context from the job</title>
<updated>2018-07-16T21:11:52Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-07-13T07:58:49Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=eb3961a57424a5c3dae44576d1c88e64a818d871'/>
<id>urn:sha1:eb3961a57424a5c3dae44576d1c88e64a818d871</id>
<content type='text'>
Can be obtained directly from the fence as well.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Junwei Zhang &lt;Jerry.Zhang@amd.com&gt;
Acked-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fix user fence write race condition</title>
<updated>2018-07-05T21:39:57Z</updated>
<author>
<name>Nicolai Hähnle</name>
<email>nicolai.haehnle@amd.com</email>
</author>
<published>2018-06-29T11:23:25Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=9fc15f5fc836712b173f04e143b8d77fdded1a37'/>
<id>urn:sha1:9fc15f5fc836712b173f04e143b8d77fdded1a37</id>
<content type='text'>
The buffer object backing the user fence is reserved using the non-user
fence, i.e., as soon as the non-user fence is signaled, the user fence
buffer object can be moved or even destroyed.

Therefore, emit the user fence first.

Both fences have the same cache invalidation behavior, so this should
have no user-visible effect.

Signed-off-by: Nicolai Hähnle &lt;nicolai.haehnle@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: enable vcn jpeg ib test</title>
<updated>2018-06-15T17:20:38Z</updated>
<author>
<name>Boyuan Zhang</name>
<email>boyuan.zhang@amd.com</email>
</author>
<published>2018-05-01T18:40:24Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=5b2329b61875e7118a599f2f1cf6d23c8ac75a69'/>
<id>urn:sha1:5b2329b61875e7118a599f2f1cf6d23c8ac75a69</id>
<content type='text'>
Enable vcn jpeg ib ring test in amdgpu_ib.c

Signed-off-by: Boyuan Zhang &lt;boyuan.zhang@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: optionally do a writeback but don't invalidate TC for IB fences</title>
<updated>2018-05-15T18:43:32Z</updated>
<author>
<name>Marek Olšák</name>
<email>marek.olsak@amd.com</email>
</author>
<published>2018-04-03T17:05:03Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=d240cd9eddd943dbe0267d081697195ff1e90b65'/>
<id>urn:sha1:d240cd9eddd943dbe0267d081697195ff1e90b65</id>
<content type='text'>
There is a new IB flag that enables this new behavior.
Full invalidation is unnecessary for RELEASE_MEM and doesn't make sense
when draw calls from two adjacent gfx IBs run in parallel. This will be
the new default for Mesa.

v2: bump the version

Signed-off-by: Marek Olšák &lt;marek.olsak@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: cleanup SA inti and fini(v2)</title>
<updated>2018-02-28T19:18:07Z</updated>
<author>
<name>Monk Liu</name>
<email>Monk.Liu@amd.com</email>
</author>
<published>2018-01-26T08:57:25Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=bffe07b8b97d7faaf3d291129aafef2ee8a80e90'/>
<id>urn:sha1:bffe07b8b97d7faaf3d291129aafef2ee8a80e90</id>
<content type='text'>
should use bo_create_kernel instead of split to two
function that create and pin the SA bo

issue:
before this patch, there are DMAR read error in host
side when running SRIOV test, the DMAR address dropped
in the range of SA bo.

fix:
after this cleanups of SA init and fini, above DMAR
eror gone.

v2:
keep sa_bo's fini instead of suspend, to keep
reporting error

Signed-off-by: Monk Liu &lt;Monk.Liu@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: adjust timeout for ib_ring_tests(v2)</title>
<updated>2018-02-28T19:18:07Z</updated>
<author>
<name>Monk Liu</name>
<email>Monk.Liu@amd.com</email>
</author>
<published>2018-01-23T10:26:20Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=dbf797655a43c6318ebb90b899e6583fcadc6472'/>
<id>urn:sha1:dbf797655a43c6318ebb90b899e6583fcadc6472</id>
<content type='text'>
issue:
sometime GFX/MM ib test hit timeout under SRIOV env, root cause
is that engine doesn't come back soon enough so the current
IB test considered as timed out.

fix:
for SRIOV GFX IB test wait time need to be expanded a lot during
SRIOV runtimei mode since it couldn't really begin before GFX engine
come back.

for SRIOV MM IB test it always need more time since MM scheduling
is not go together with GFX engine, it is controled by h/w MM
scheduler so no matter runtime or exclusive mode MM IB test
always need more time.

v2:
use ring type instead of idx to judge

Signed-off-by: Monk Liu &lt;Monk.Liu@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: cond_exec only for schedule with a job</title>
<updated>2018-02-28T19:18:04Z</updated>
<author>
<name>Monk Liu</name>
<email>Monk.Liu@amd.com</email>
</author>
<published>2018-01-19T11:06:31Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=113890ee99575a5340ab8729b207e48aaac2eb06'/>
<id>urn:sha1:113890ee99575a5340ab8729b207e48aaac2eb06</id>
<content type='text'>
issue:
under SR-IOV sometimes the iB test will fail on
gfx ring

fix:
with cond_exec inserted in RB the gfx engine would
skip part packets if RLCV issue PREEMPT on gfx engine
if gfx engine is prior to COND_EXEC packet, this is
okay for regular command from UMD, but for the ib test
since the whole dma format doesn't support PREEMPT
so must remove the COND_EXEC from it.

Signed-off-by: Monk Liu &lt;Monk.Liu@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: remove now superflous *_hdp operation</title>
<updated>2018-02-19T19:18:22Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-01-19T14:19:16Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=2ee150cda7bdc766cf9baca3534f3a2c0b0e8357'/>
<id>urn:sha1:2ee150cda7bdc766cf9baca3534f3a2c0b0e8357</id>
<content type='text'>
All HDP invalidation and most flush can now be replaced by the generic
ASIC function.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Acked-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fallback to generic HDP operation</title>
<updated>2018-02-19T19:18:21Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-01-19T13:21:47Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=1b9d17db1cb103f56a69d8610d7339fb0a2a90cc'/>
<id>urn:sha1:1b9d17db1cb103f56a69d8610d7339fb0a2a90cc</id>
<content type='text'>
When ring special operations aren't available we can fallback to the
generic ASIC operations.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Acked-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
