<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c, branch v4.7</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v4.7</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v4.7'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2016-06-13T22:59:17Z</updated>
<entry>
<title>Revert "drm/amdgpu: add pipeline sync while vmid switch in same ctx"</title>
<updated>2016-06-13T22:59:17Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2016-06-13T22:59:17Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=7c4021d403ca72ce52d39c17d8154974521a82be'/>
<id>urn:sha1:7c4021d403ca72ce52d39c17d8154974521a82be</id>
<content type='text'>
This reverts commit 2ba272d7bde27e1db2cf1c6cee49b01b7ea08989.

The issue fixed by this patch is specific to compute rings and the
previous patch was enough.  Additionally, this patch as been traced
to strange behavior on some CZ systems so we might as well drop it.
</content>
</entry>
<entry>
<title>drm/amdgpu: add pipeline sync while vmid switch in same ctx</title>
<updated>2016-06-09T14:49:01Z</updated>
<author>
<name>Chunming Zhou</name>
<email>David1.Zhou@amd.com</email>
</author>
<published>2016-04-27T10:07:41Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=2ba272d7bde27e1db2cf1c6cee49b01b7ea08989'/>
<id>urn:sha1:2ba272d7bde27e1db2cf1c6cee49b01b7ea08989</id>
<content type='text'>
Since vmid-mgr supports vmid sharing in one vm, the same ctx could
get different vmids for two emits without vm flush, vm_flush could
be done in another ring.

Signed-off-by: Chunming Zhou &lt;David1.Zhou@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fix and cleanup user fence handling v2</title>
<updated>2016-05-11T17:30:32Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2016-05-06T20:14:00Z</published>
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<id>urn:sha1:758ac17f963f3497aae4e767d3a9eb68fea71f71</id>
<content type='text'>
We leaked the BO in the error pass, additional to that we only have
one user fence for all IBs in a job.

v2: remove white space changes

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: move VM fields into job</title>
<updated>2016-05-11T17:30:31Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2016-05-06T15:50:03Z</published>
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<id>urn:sha1:d88bf583bd06eecb31f82871c90ef6a5a09b5766</id>
<content type='text'>
They are the same for all IBs.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: move the context from the IBs into the job</title>
<updated>2016-05-11T17:30:31Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2016-05-06T13:57:42Z</published>
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<id>urn:sha1:92f250989b7098f4b52d50183a7b2fc4e010731b</id>
<content type='text'>
We only have one context for all IBs.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: move context switch handling into common code v2</title>
<updated>2016-05-11T17:30:30Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2016-05-06T13:31:19Z</published>
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<id>urn:sha1:f153d2867bf74f84d47f67c377a8e3a34865e562</id>
<content type='text'>
It was a source of bugs to repeat that in each IP version.

v2: rename parameter

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: move preamble IB handling into common code</title>
<updated>2016-05-11T17:30:30Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2016-05-06T12:52:57Z</published>
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<id>urn:sha1:9f8fb5a2b339ba83493991ca8f1173a939a696d3</id>
<content type='text'>
This fixes the handling which was completely broken when you
ad more than one preamble IB.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: use fence_context to judge ctx switch v2</title>
<updated>2016-05-11T16:31:27Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2016-05-03T13:17:40Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=aa3b73f67bda66637f17c3d847a8a36d3649f3f8'/>
<id>urn:sha1:aa3b73f67bda66637f17c3d847a8a36d3649f3f8</id>
<content type='text'>
Use of the ctx pointer is not safe, because they are likely already
be assigned to another ctx when doing comparing.

v2: recreate from scratch, avoid all unnecessary changes.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Monk.Liu &lt;monk.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: two minor 80 char fixes</title>
<updated>2016-05-11T16:31:18Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2016-05-03T16:46:19Z</published>
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<id>urn:sha1:4d9c514d8ccff2b4bd0db5d3e178c0c0b3f3bc77</id>
<content type='text'>
Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Tom St Denis &lt;tom.stdenis@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: hdp flush&amp;inval should always do</title>
<updated>2016-05-11T16:31:17Z</updated>
<author>
<name>Monk Liu</name>
<email>Monk.Liu@amd.com</email>
</author>
<published>2016-05-04T08:27:41Z</published>
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<id>urn:sha1:794ff5710eb1d8bea4acc79cd005f6342623ec46</id>
<content type='text'>
This fixes Tonga vm-fault issue when running disaster
(a multiple context GL heavy tests),
We should always flush &amp; invalidate hdp no matter vm
used or not.

Signed-off-by: Monk Liu &lt;Monk.Liu@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Chunming Zhou &lt;David1.Zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
</feed>
