linux/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c, branch v6.3

drm/amdgpu: MCBP based on DRM scheduler (v9)

2022-12-02T15:04:51Z

Trigger Mid-Command Buffer Preemption according to the priority of the software rings and the hw fence signalling condition. The muxer saves the locations of the indirect buffer frames from the software ring together with the fence sequence number in its fifo queue, and pops out those records when the fences are signalled. The locations are used to resubmit packages in preemption scenarios by coping the chunks from the software ring. v2: Update comment style. v3: Fix conflict caused by previous modifications. v4: Remove unnecessary prints. v5: Fix corner cases for resubmission cases. v6: Refactor functions for resubmission, calling fence_process in irq handler. v7: Solve conflict for removing amdgpu_sw_ring.c. v8: Add time threshold to judge if preemption request is needed. v9: Correct comment spelling. Set fence emit timestamp before rsu assignment. Cc: Christian Koenig Cc: Luben Tuikov Cc: Andrey Grodzovsky Cc: Michel Dänzer Signed-off-by: Jiadong.Zhu Acked-by: Luben Tuikov Acked-by: Huang Rui Acked-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: move explicit sync check into the CS

2022-11-03T11:45:20Z

This moves the memory allocation out of the critical code path. Signed-off-by: Christian König Reviewed-by: Luben Tuikov Link: https://patchwork.freedesktop.org/patch/msgid/20221014084641.128280-8-christian.koenig@amd.com

drm/amdgpu: skip kiq ib tests if mes enabled

2022-05-04T14:43:52Z

For kiq conflicts with mes, skip kiq ib tests. Signed-off-by: Jack Xiao Acked-by: Christian König Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher

drm/amdgpu: skip some checking for mes queue ib submission

2022-05-04T14:43:52Z

Skip some checking for mes queue ib submission. Signed-off-by: Jack Xiao Acked-by: Christian König Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher

drm/amdgpu: only allow secure submission on rings which support that

2022-03-15T18:42:27Z

Only GFX ring, SDMA ring and VCN decode ring support secure submission at the moment. Suggested-by: Christian König Signed-off-by: Lang Yu Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: Increase direct IB pool size

2021-09-14T19:56:49Z

Direct IB pool is used for vce/vcn IB extra msg too. Increase its size to AMDGPU_IB_POOL_SIZE. v2: Squash in unused variable removal Signed-off-by: xinhui pan Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amd/amdgpu embed hw_fence into amdgpu_job

2021-08-16T19:16:58Z

Why: Previously hw fence is alloced separately with job. It caused historical lifetime issues and corner cases. The ideal situation is to take fence to manage both job and fence's lifetime, and simplify the design of gpu-scheduler. How: We propose to embed hw_fence into amdgpu_job. 1. We cover the normal job submission by this method. 2. For ib_test, and submit without a parent job keep the legacy way to create a hw fence separately. v2: use AMDGPU_FENCE_FLAG_EMBED_IN_JOB_BIT to show that the fence is embedded in a job. v3: remove redundant variable ring in amdgpu_job v4: add tdr sequence support for this feature. Add a job_run_counter to indicate whether this job is a resubmit job. v5 add missing handling in amdgpu_fence_enable_signaling Signed-off-by: Jingwen Chen Signed-off-by: Jack Zhang Reviewed-by: Andrey Grodzovsky Reviewed by: Monk Liu Signed-off-by: Alex Deucher

drm/amdgpu: Don't flush/invalidate HDP for APUs and A+A

2021-06-04T20:02:38Z

Integrate two generic functions to determine if HDP flush is needed for all Asics. Signed-off-by: Eric Huang Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: remove unsafe optimization to drop preamble ib

2021-06-02T02:55:39Z

Take the situation with gfxoff, the optimization may cause corrupt CE ram contents. In addition emit_cntxcntl callback has similar optimization which firmware can handle properly even for power feature. Signed-off-by: Jiansong Chen Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher

drm/amdgpu: fix no full coverage issue for gprs initialization

2021-04-29T03:36:05Z

The wave's number per simd in aldebaran is changed to 8, so it is impossible to use old algorithm to initiate all sgprs with one threadgroup. The new algorithm firstly use three threadgroups to initiate most sgprs simultaneously and then use another threadgroup with 4 waves to cover other uninitiated sgprs. v2: Add more description about the new algorithm to clear sgprs and add some comment for shader binaries Signed-off-by: Dennis Li Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher