<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c, branch v4.19</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v4.19</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v4.19'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2018-07-31T21:58:18Z</updated>
<entry>
<title>drm/amdgpu: nuke amdgpu_bo_list_free</title>
<updated>2018-07-31T21:58:18Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-07-30T12:17:41Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=a0f208453b97565dab8c334ff013aa5ab3c66d0c'/>
<id>urn:sha1:a0f208453b97565dab8c334ff013aa5ab3c66d0c</id>
<content type='text'>
The RCU grace period is harmless and avoiding it is not worth the effort
of doubling the implementation.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Chunming  Zhou &lt;david1.zhou@amd.com&gt;
Reviewed-by: Huang Rui &lt;ray.huang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: implement harvesting support for UVD 7.2 (v3)</title>
<updated>2018-07-27T14:07:44Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2018-07-25T20:11:34Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=f1e582ebfd703ea01dc4caf4d339b7c84ec3ff29'/>
<id>urn:sha1:f1e582ebfd703ea01dc4caf4d339b7c84ec3ff29</id>
<content type='text'>
Properly handle cases where one or more instance of the IP
block may be harvested.

v2: make sure ip_num_rings is initialized amdgpu_queue_mgr.c
v3: rebase on Christian's UVD changes, drop unused var

Reviewed-by: James Zhu &lt;James.Zhu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: expose only the first UVD instance for now</title>
<updated>2018-07-25T20:05:32Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-07-18T12:17:59Z</published>
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<id>urn:sha1:4d4831a3dae3161ab5a96694462eff708dfefc71</id>
<content type='text'>
Going to completely rework the context to ring mapping with Nayan's GSoC
work, but for now just stopping to expose the second UVD instance should
do it.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: clean up coding style a bit</title>
<updated>2018-07-25T20:05:08Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-07-18T11:58:16Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=f8a91d45553ab581964f40b1e46bdf3d0974d339'/>
<id>urn:sha1:f8a91d45553ab581964f40b1e46bdf3d0974d339</id>
<content type='text'>
No need to bitcast a boolean and even if we should use "!!" instead.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Make pin_size values atomic</title>
<updated>2018-07-13T19:46:21Z</updated>
<author>
<name>Michel Dänzer</name>
<email>michel.daenzer@amd.com</email>
</author>
<published>2018-07-11T10:00:40Z</published>
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<id>urn:sha1:a5ccfe5c20740f2fbf00291490cdf8d2373ec255</id>
<content type='text'>
Concurrent execution of the non-atomic arithmetic could result in
completely bogus values.

v2:
* Rebased on v2 of the previous patch

Cc: stable@vger.kernel.org
Bugzilla: https://bugs.freedesktop.org/106872
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Michel Dänzer &lt;michel.daenzer@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Keep track of amount of pinned CPU visible VRAM</title>
<updated>2018-07-13T19:46:11Z</updated>
<author>
<name>Michel Dänzer</name>
<email>michel.daenzer@amd.com</email>
</author>
<published>2018-07-11T10:06:31Z</published>
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<id>urn:sha1:ddc21af4d0f37f42b33c54cb69b215997fe5b082</id>
<content type='text'>
Instead of CPU invisible VRAM. Preparation for the following, no
functional change intended.

v2:
* Also change amdgpu_vram_mgr_bo_invisible_size to
  amdgpu_vram_mgr_bo_visible_size, allowing further simplification
  (Christian König)

Cc: stable@vger.kernel.org
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Michel Dänzer &lt;michel.daenzer@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: update ib_start/size_alignment same as windows used</title>
<updated>2018-06-19T18:17:39Z</updated>
<author>
<name>Chunming Zhou</name>
<email>david1.zhou@amd.com</email>
</author>
<published>2018-06-15T06:39:57Z</published>
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<id>urn:sha1:8e2c7ad99dce3f4242fa0d0d5950ca3ba0f212c3</id>
<content type='text'>
PAGE_SIZE for start_alignment is far much than hw requirement,
And now, update to expereince value from window side.

Signed-off-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Acked-by: Marek Olšák &lt;marek.olsak@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Acked-by: Junwei Zhang &lt;Jerry.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add AMDGPU_HW_IP_VCN_JPEG to info query</title>
<updated>2018-06-15T17:20:39Z</updated>
<author>
<name>Boyuan Zhang</name>
<email>boyuan.zhang@amd.com</email>
</author>
<published>2018-05-01T18:58:25Z</published>
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<id>urn:sha1:4bafe44024295f087fd633a16e100a34ca363e7c</id>
<content type='text'>
Add AMDGPU_HW_IP_VCN_JPEG to info query

Signed-off-by: Boyuan Zhang &lt;boyuan.zhang@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: move amdgpu_ctx_mgr_entity_fini to f_ops flush hook (V4)</title>
<updated>2018-06-15T17:20:33Z</updated>
<author>
<name>Andrey Grodzovsky</name>
<email>andrey.grodzovsky@amd.com</email>
</author>
<published>2018-05-30T19:28:52Z</published>
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<id>urn:sha1:48ad368a8a3ab2fd3c2bc2ccccc6e29b1acda1bb</id>
<content type='text'>
With this we can now terminate jobs enqueue into SW queue the moment
the task is being killed instead of waiting for last user of
drm file to release it.

Also stop checking for kref_read(&amp;ctx-&gt;refcount) == 1 when
calling drm_sched_entity_do_release since other task
might still hold a reference to this entity but we don't
care since KILL means terminate job submission regardless
of what other tasks are doing.

v2:
Use returned remaining timeout as parameter for the next call.
Rebase.

v3:
Switch to working with jiffies.
Streamline remainder TO usage.
Rebase.

v4:
Rebase.

Signed-off-by: Andrey Grodzovsky &lt;andrey.grodzovsky@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/vg20:Restruct uvd.inst to support multiple instances</title>
<updated>2018-05-18T21:08:12Z</updated>
<author>
<name>James Zhu</name>
<email>James.Zhu@amd.com</email>
</author>
<published>2018-05-15T19:31:24Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=10dd74eac4dba963bfa97f5092040aa75ff742d6'/>
<id>urn:sha1:10dd74eac4dba963bfa97f5092040aa75ff742d6</id>
<content type='text'>
Vega20 has dual-UVD. Need add multiple instances support for uvd.
Restruct uvd.inst, using uvd.inst[0] to replace uvd.inst-&gt;.
Repurpose amdgpu_ring::me for instance index, and initialize to 0.
There are no any logical changes here.

Signed-off-by: James Zhu &lt;James.Zhu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
