<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c, branch v6.4</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v6.4</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v6.4'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2023-04-11T22:03:21Z</updated>
<entry>
<title>drm/amd/amdgpu: introduce gc_*_mes_2.bin v2</title>
<updated>2023-04-11T22:03:21Z</updated>
<author>
<name>Jack Xiao</name>
<email>Jack.Xiao@amd.com</email>
</author>
<published>2023-03-24T08:55:15Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=97998b893c3000b27a780a4982e16cfc8f4ea555'/>
<id>urn:sha1:97998b893c3000b27a780a4982e16cfc8f4ea555</id>
<content type='text'>
To avoid new mes fw running with old driver, rename
mes schq fw to gc_*_mes_2.bin.

v2: add MODULE_FIRMWARE declaration
v3: squash in fixup patch

Signed-off-by: Jack Xiao &lt;Jack.Xiao@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: limit one queue per gang</title>
<updated>2023-03-22T05:07:04Z</updated>
<author>
<name>Jack Xiao</name>
<email>Jack.Xiao@amd.com</email>
</author>
<published>2023-03-22T01:31:16Z</published>
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<id>urn:sha1:5ee33d905f89c18d4b33da6e5eefdae6060502df</id>
<content type='text'>
Limit one queue per gang in mes self test,
due to mes schq fw change.

Signed-off-by: Jack Xiao &lt;Jack.Xiao@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/amdgpu/amdgpu_mes: Ensure amdgpu_bo_create_kernel()'s return value is checked</title>
<updated>2023-03-22T04:48:00Z</updated>
<author>
<name>Lee Jones</name>
<email>lee@kernel.org</email>
</author>
<published>2023-03-17T08:16:58Z</published>
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<id>urn:sha1:0b9ff428de417423ca87f77dd6e836be967831a5</id>
<content type='text'>
Fixes the following W=1 kernel build warning(s):

 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c: In function ‘amdgpu_mes_ctx_alloc_meta_data’:
 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c:1099:13: warning: variable ‘r’ set but not used [-Wunused-but-set-variable]

Cc: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: "Christian König" &lt;christian.koenig@amd.com&gt;
Cc: "Pan, Xinhui" &lt;Xinhui.Pan@amd.com&gt;
Cc: David Airlie &lt;airlied@gmail.com&gt;
Cc: Daniel Vetter &lt;daniel@ffwll.ch&gt;
Cc: Sumit Semwal &lt;sumit.semwal@linaro.org&gt;
Cc: Jack Xiao &lt;Jack.Xiao@amd.com&gt;
Cc: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Cc: linux-media@vger.kernel.org
Cc: linaro-mm-sig@lists.linaro.org
Signed-off-by: Lee Jones &lt;lee@kernel.org&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd: Use `amdgpu_ucode_*` helpers for MES</title>
<updated>2023-01-09T22:02:18Z</updated>
<author>
<name>Mario Limonciello</name>
<email>mario.limonciello@amd.com</email>
</author>
<published>2023-01-03T20:12:37Z</published>
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<id>urn:sha1:11e0b0067ec0707e8e598a5f9a547ab618ae7982</id>
<content type='text'>
The `amdgpu_ucode_request` helper will ensure that the return code for
missing firmware is -ENODEV so that early_init can fail.

The `amdgpu_ucode_release` helper provides symmetry for releasing firmware.

Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd: Load MES microcode during early_init</title>
<updated>2023-01-09T22:02:18Z</updated>
<author>
<name>Mario Limonciello</name>
<email>mario.limonciello@amd.com</email>
</author>
<published>2022-12-28T07:28:40Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=cc42e76e7de5190a7da5dac9d7b2bbb458e050bf'/>
<id>urn:sha1:cc42e76e7de5190a7da5dac9d7b2bbb458e050bf</id>
<content type='text'>
Add an early_init phase to MES for fetching and validating microcode
from the filesystem.

If MES microcode is required but not available during early init, the
firmware framebuffer will have already been released and the screen will
freeze.

Move the request for MES microcode into the early_init phase
so that if it's not available, early_init will fail.

Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/mes: zero the sdma_hqd_mask of 2nd SDMA engine for SDMA 6.0.1</title>
<updated>2022-09-14T19:00:34Z</updated>
<author>
<name>Yifan Zhang</name>
<email>yifan1.zhang@amd.com</email>
</author>
<published>2022-08-30T15:18:47Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=0af4ed0c329ebb4cef95fda4fcdbfcdea0255442'/>
<id>urn:sha1:0af4ed0c329ebb4cef95fda4fcdbfcdea0255442</id>
<content type='text'>
there is only one SDMA engine in SDMA 6.0.1, the sdma_hqd_mask has to be
zeroed for the 2nd engine, otherwise MES scheduler will consider 2nd
engine exists and map/unmap SDMA queues to the non-existent engine.

Signed-off-by: Yifan Zhang &lt;yifan1.zhang@amd.com&gt;
Reviewed-by: Tim Huang &lt;Tim.Huang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/mes: ring aggregatged doorbell when mes queue is unmapped</title>
<updated>2022-07-13T15:25:17Z</updated>
<author>
<name>Le Ma</name>
<email>le.ma@amd.com</email>
</author>
<published>2020-10-30T03:26:23Z</published>
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<id>urn:sha1:2d7a1f71837c0922645143cc270b5a4834595544</id>
<content type='text'>
Ring aggregated doorbel to make unmapped queue scheduled in mes firmware.

Signed-off-by: Le Ma &lt;le.ma@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Jack Xiao &lt;Jack.Xiao@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/mes: init aggregated doorbell</title>
<updated>2022-07-13T15:25:17Z</updated>
<author>
<name>Le Ma</name>
<email>le.ma@amd.com</email>
</author>
<published>2020-10-30T03:24:07Z</published>
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<id>urn:sha1:0fe6906203d02d050e86b3398219df7bd9e8fe47</id>
<content type='text'>
Allocate and enable aggregated doorbell.

Signed-off-by: Le Ma &lt;le.ma@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Jack Xiao &lt;Jack.Xiao@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/mes: fix bo va unmap issue in mes</title>
<updated>2022-07-12T14:03:20Z</updated>
<author>
<name>Jack Xiao</name>
<email>Jack.Xiao@amd.com</email>
</author>
<published>2020-09-09T10:32:36Z</published>
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<id>urn:sha1:737dad0b5d609f464cae73292de646d3d016ec73</id>
<content type='text'>
Need reserve buffers before unmap mes ctx bo va.

v2: fix removal of dma_resv_excl_fence() (Alex)
v3: fix dma_resv_usage (Alex)

Signed-off-by: Jack Xiao &lt;Jack.Xiao@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/mes: fix mes submission in atomic context</title>
<updated>2022-07-08T22:25:56Z</updated>
<author>
<name>Jack Xiao</name>
<email>Jack.Xiao@amd.com</email>
</author>
<published>2022-07-07T12:57:34Z</published>
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<id>urn:sha1:35ba8850b673050b71b17c1421079031f4fda319</id>
<content type='text'>
For some cases (accessing registers, unmap legacy queue), it needs
access mes in atomic context. Use spinlock to protect agaist mes
ring buffer race condition.

Signed-off-by: Jack Xiao &lt;Jack.Xiao@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
