<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c, branch v5.7</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.7</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.7'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2020-04-07T18:07:41Z</updated>
<entry>
<title>drm/amdgpu/psp: dont warn on missing optional TA's</title>
<updated>2020-04-07T18:07:41Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2020-04-03T16:25:48Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=8f0622a19bef2dc09b511ccf8c536067521ade83'/>
<id>urn:sha1:8f0622a19bef2dc09b511ccf8c536067521ade83</id>
<content type='text'>
Replace dev_warn() with dev_info() and note that they are
optional to avoid confusing users.

The RAS TAs only exist on server boards and the HDCP and DTM
TAs only exist on client boards.  They are optional either way.

Acked-by: Nirmoy Das &lt;nirmoy.das@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>Revert "drm/amdgpu: add CAP fw loading"</title>
<updated>2020-03-25T20:58:40Z</updated>
<author>
<name>Zhigang Luo</name>
<email>zhigang.luo@amd.com</email>
</author>
<published>2020-03-25T19:34:21Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=728b3d0533a4c39ed36a33e36148544b2ec770be'/>
<id>urn:sha1:728b3d0533a4c39ed36a33e36148544b2ec770be</id>
<content type='text'>
This reverts commit 29e2501f8a64fa2fa8f6fe4be53cce5a5a4fe79f.

Signed-off-by: Zhigang Luo &lt;zhigang.luo@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add CAP fw loading</title>
<updated>2020-03-19T04:03:05Z</updated>
<author>
<name>Zhigang Luo</name>
<email>zhigang.luo@amd.com</email>
</author>
<published>2020-02-26T15:30:13Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=29e2501f8a64fa2fa8f6fe4be53cce5a5a4fe79f'/>
<id>urn:sha1:29e2501f8a64fa2fa8f6fe4be53cce5a5a4fe79f</id>
<content type='text'>
The CAP fw is for enabling driver compatibility. Currently, it only
enabled for vega10 VF.

Signed-off-by: Zhigang Luo &lt;zhigang.luo@amd.com&gt;
Reviewed-by: Shaoyun Liu &lt;Shaoyun.Liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: resolve failed error inject msg</title>
<updated>2020-03-13T15:52:33Z</updated>
<author>
<name>John Clements</name>
<email>john.clements@amd.com</email>
</author>
<published>2020-03-11T03:51:02Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=c2c6f816a8155e8f33a280b392777a0a8b913ac4'/>
<id>urn:sha1:c2c6f816a8155e8f33a280b392777a0a8b913ac4</id>
<content type='text'>
invoking an error injection successfully will cause an at_event intterrupt that

will occur before the invoke sequence can complete causing an invalid error

Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: John Clements &lt;john.clements@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Fix GPU reset error.</title>
<updated>2020-03-06T19:32:24Z</updated>
<author>
<name>Andrey Grodzovsky</name>
<email>andrey.grodzovsky@amd.com</email>
</author>
<published>2020-03-04T21:36:42Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=90f88cdd7c8d6a6a3be18353d6a03798f9a03168'/>
<id>urn:sha1:90f88cdd7c8d6a6a3be18353d6a03798f9a03168</id>
<content type='text'>
Problem:
During GU reset PSP's sysfs was being wrongly reinitilized
during call to amdgpu_device_ip_late_init which was failing
with duplicate error.
Fix:
Move psp_sysfs_init to psp_sw_init to avoid this. Add guards
in sysfs file's read and write hook agains premature call
if PSP is not finished initialization.

Signed-off-by: Andrey Grodzovsky &lt;andrey.grodzovsky@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Wrap clflush_cache_range with x86 ifdef</title>
<updated>2020-03-05T05:33:30Z</updated>
<author>
<name>Andrey Grodzovsky</name>
<email>andrey.grodzovsky@amd.com</email>
</author>
<published>2020-03-04T18:07:00Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=6863d60732acf57c86e70558640ae357a83bce0f'/>
<id>urn:sha1:6863d60732acf57c86e70558640ae357a83bce0f</id>
<content type='text'>
To avoid compile errors on other platforms.

Signed-off-by: Andrey Grodzovsky &lt;andrey.grodzovsky@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add support for USBC PD FW download</title>
<updated>2020-03-05T05:33:24Z</updated>
<author>
<name>Andrey Grodzovsky</name>
<email>andrey.grodzovsky@amd.com</email>
</author>
<published>2019-12-19T19:58:18Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=57430471e2fa60a412e220fa3014567e792aaa6f'/>
<id>urn:sha1:57430471e2fa60a412e220fa3014567e792aaa6f</id>
<content type='text'>
Starts USBC PD FW download and reads back the latest FW version.

v2:
Move sysfs file creation to late init
Add locking around PSP calls to avoid concurrent access to PSP's C2P registers

Signed-off-by: Andrey Grodzovsky &lt;andrey.grodzovsky@amd.com&gt;
Reviewed-by: Luben Tuikov &lt;luben.tuikov@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: update psp firmwares loading sequence V2</title>
<updated>2020-02-26T19:17:32Z</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2020-02-24T09:06:41Z</published>
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<id>urn:sha1:995da6cc4c47c05b16f2099caf99328cd9c719e1</id>
<content type='text'>
For those ASICs with DF Cstate management centralized to PMFW,
TMR setup should be performed between pmfw loading and other
non-psp firmwares loading.

V2: skip possible SMU firmware reloading

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fix psp ucode not loaded in bare-metal</title>
<updated>2020-02-25T16:01:49Z</updated>
<author>
<name>Monk Liu</name>
<email>Monk.Liu@amd.com</email>
</author>
<published>2020-02-21T06:54:29Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=82c4ebfa35140a75259eed435134e150ac8e459a'/>
<id>urn:sha1:82c4ebfa35140a75259eed435134e150ac8e459a</id>
<content type='text'>
for bare-metal we alawys need to load sys/sos/kdb

Signed-off-by: Monk Liu &lt;Monk.Liu@amd.com&gt;
Reviewed-by: Evan Quan &lt;evan.quan@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: cleanup some incorrect reg access for SRIOV</title>
<updated>2020-02-25T16:01:25Z</updated>
<author>
<name>Monk Liu</name>
<email>Monk.Liu@amd.com</email>
</author>
<published>2020-01-23T09:25:38Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=f77a9c920aa2b103abe25b2a0294acbe8f2ba70f'/>
<id>urn:sha1:f77a9c920aa2b103abe25b2a0294acbe8f2ba70f</id>
<content type='text'>
1)
we shouldn't load PSP kdb and sys/sos for VF, they are
supposed to be handled by hypervisor

2)
ih reroute doesn't work on VF thus we should avoid calling
it, besides VF should not use those PSP register sets for PF

3)
shouldn't load SMU ucode under SRIOV, otherwise PSP would report
error

Signed-off-by: Monk Liu &lt;Monk.Liu@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
