<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c, branch v4.19</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v4.19</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v4.19'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2018-07-18T21:18:43Z</updated>
<entry>
<title>drm/amdgpu: allow for more flexible priority handling</title>
<updated>2018-07-18T21:18:43Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-07-16T11:47:34Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=9d46f32bdd3e9d4bf435c5ae50f72fb475bf0620'/>
<id>urn:sha1:9d46f32bdd3e9d4bf435c5ae50f72fb475bf0620</id>
<content type='text'>
Allow to call amdgpu_ring_priority_get() after pushing the ring to the
scheduler.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: define and add extra dword for jpeg ring</title>
<updated>2018-06-15T17:20:37Z</updated>
<author>
<name>Boyuan Zhang</name>
<email>boyuan.zhang@amd.com</email>
</author>
<published>2018-06-01T16:30:17Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=c8c1a1d2ef040d2661fc9c7f0b32aec5b1058ae3'/>
<id>urn:sha1:c8c1a1d2ef040d2661fc9c7f0b32aec5b1058ae3</id>
<content type='text'>
Define extra dword for jpeg ring. Jpeg ring will allocate extra dword to store
the patch commands for fixing the known issue.

v2: dropping extra_dw for rings other than jpeg.

Signed-off-by: Boyuan Zhang &lt;boyuan.zhang@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/vg20:Restruct uvd.inst to support multiple instances</title>
<updated>2018-05-18T21:08:12Z</updated>
<author>
<name>James Zhu</name>
<email>James.Zhu@amd.com</email>
</author>
<published>2018-05-15T19:31:24Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=10dd74eac4dba963bfa97f5092040aa75ff742d6'/>
<id>urn:sha1:10dd74eac4dba963bfa97f5092040aa75ff742d6</id>
<content type='text'>
Vega20 has dual-UVD. Need add multiple instances support for uvd.
Restruct uvd.inst, using uvd.inst[0] to replace uvd.inst-&gt;.
Repurpose amdgpu_ring::me for instance index, and initialize to 0.
There are no any logical changes here.

Signed-off-by: James Zhu &lt;James.Zhu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add emit_reg_write_reg_wait ring callback</title>
<updated>2018-05-15T18:43:13Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2018-03-27T16:58:14Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=828536385ab0d25b5ddd7153347df04ea3a6961d'/>
<id>urn:sha1:828536385ab0d25b5ddd7153347df04ea3a6961d</id>
<content type='text'>
This callback writes a value to a register and then reads
back another register and waits for a value in a single
operation.

Provide a helper function using two operations for engines
that don't support this opertion.

Reviewed-by: Huang Rui &lt;ray.huang@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: Mask rptr as well in ring debugfs</title>
<updated>2018-03-01T17:04:17Z</updated>
<author>
<name>Tom St Denis</name>
<email>tom.stdenis@amd.com</email>
</author>
<published>2018-03-01T14:39:57Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=9c5c71bbed4132a3a5f200064914db768c88302a'/>
<id>urn:sha1:9c5c71bbed4132a3a5f200064914db768c88302a</id>
<content type='text'>
The read/write pointers on sdma4 devices increment
beyond the ring size and should be masked.  Tested
on my Ryzen 2400G.

Signed-off-by: Tom St Denis &lt;tom.stdenis@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: cache the fence to wait for a VMID</title>
<updated>2018-02-19T19:19:18Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-01-31T15:03:19Z</published>
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<id>urn:sha1:3af81440a9b02e2c6e244539ee567063c3d62292</id>
<content type='text'>
Beneficial when a lot of processes are waiting for VMIDs.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: rename amdgpu_wb_* functions</title>
<updated>2017-12-18T15:59:07Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2017-12-14T21:03:43Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=131b4b3686b701079e8fb82eb9384c8acdd3fc72'/>
<id>urn:sha1:131b4b3686b701079e8fb82eb9384c8acdd3fc72</id>
<content type='text'>
add device for consistency.

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm: move amd_gpu_scheduler into common location</title>
<updated>2017-12-07T16:51:56Z</updated>
<author>
<name>Lucas Stach</name>
<email>l.stach@pengutronix.de</email>
</author>
<published>2017-12-06T16:49:39Z</published>
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<id>urn:sha1:1b1f42d8fde4fef1ed7873bf5aa91755f8c3de35</id>
<content type='text'>
This moves and renames the AMDGPU scheduler to a common location in DRM
in order to facilitate re-use by other drivers. This is mostly a straight
forward rename with no code changes.

One notable exception is the function to_drm_sched_fence(), which is no
longer a inline header function to avoid the need to export the
drm_sched_fence_ops_scheduled and drm_sched_fence_ops_finished structures.

Reviewed-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Tested-by: Dieter Nützel &lt;Dieter@nuetzel-hh.de&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Lucas Stach &lt;l.stach@pengutronix.de&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: bypass lru touch for KIQ ring submission</title>
<updated>2017-11-08T22:55:14Z</updated>
<author>
<name>Pixel Ding</name>
<email>Pixel.Ding@amd.com</email>
</author>
<published>2017-11-08T02:20:01Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=dce1e131dd4dc68099ff1b70aa03cd2d0acf8639'/>
<id>urn:sha1:dce1e131dd4dc68099ff1b70aa03cd2d0acf8639</id>
<content type='text'>
KIQ ring submission is used for register accessing on SRIOV
VF that could happen both in irq enabled and irq disabled cases.
Inversion lock could happen on adev-&gt;ring_lru_list_lock, while
this operation is useless and just adds overhead in this use
case.

Signed-off-by: Pixel Ding &lt;Pixel.Ding@amd.com&gt;
Reviewed-by: Monk Liu &lt;Monk.Liu@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add framework for HW specific priority settings v9</title>
<updated>2017-10-09T20:30:21Z</updated>
<author>
<name>Andres Rodriguez</name>
<email>andresx7@gmail.com</email>
</author>
<published>2017-02-20T22:53:19Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=b2ff0e8ac4ce1fb647ae40feb4cf26bc9301e0c9'/>
<id>urn:sha1:b2ff0e8ac4ce1fb647ae40feb4cf26bc9301e0c9</id>
<content type='text'>
Add an initial framework for changing the HW priorities of rings. The
framework allows requesting priority changes for the lifetime of an
amdgpu_job. After the job completes the priority will decay to the next
lowest priority for which a request is still valid.

A new ring function set_priority() can now be populated to take care of
the HW specific programming sequence for priority changes.

v2: set priority before emitting IB, and take a ref on amdgpu_job
v3: use AMD_SCHED_PRIORITY_* instead of AMDGPU_CTX_PRIORITY_*
v4: plug amdgpu_ring_restore_priority_cb into amdgpu_job_free_cb
v5: use atomic for tracking job priorities instead of last_job
v6: rename amdgpu_ring_priority_[get/put]() and align parameters
v7: replace spinlocks with mutexes for KIQ compatibility
v8: raise ring priority during cs_ioctl, instead of job_run
v9: priority_get() before push_job()

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Andres Rodriguez &lt;andresx7@gmail.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
