<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c, branch v5.1</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.1</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.1'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2018-12-07T22:53:47Z</updated>
<entry>
<title>drm/amdgpu: Skip ring soft recovery when fence was NULL</title>
<updated>2018-12-07T22:53:47Z</updated>
<author>
<name>wentalou</name>
<email>Wentao.Lou@amd.com</email>
</author>
<published>2018-12-06T02:29:52Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=49ebca798696a6a5da02a562cd1fd0e645264511'/>
<id>urn:sha1:49ebca798696a6a5da02a562cd1fd0e645264511</id>
<content type='text'>
amdgpu_ring_soft_recovery would have Call-Trace,
when s_fence-&gt;parent was NULL inside amdgpu_job_timedout.
Check fence first, as drm_sched_hw_job_reset did.

Signed-off-by: Wentao Lou &lt;Wentao.Lou@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: further ring test cleanups</title>
<updated>2018-11-05T19:21:25Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-10-29T09:48:31Z</published>
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<id>urn:sha1:dc9eeff84c77080f545575a30062af0ac65b1eb0</id>
<content type='text'>
Move all error messages from IP specific code into the common helper.
This way we now uses the ring name in the messages instead of the index
and note which device is affected as well.

Also cleanup error handling in the IP specific code and consequently use
ETIMEDOUT when the ring test timed out.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Andrey Grodzovsky &lt;andrey.grodzovsky@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Retire amdgpu_ring.ready flag v4</title>
<updated>2018-11-05T19:21:23Z</updated>
<author>
<name>Andrey Grodzovsky</name>
<email>andrey.grodzovsky@amd.com</email>
</author>
<published>2018-10-19T20:22:48Z</published>
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<id>urn:sha1:c66ed765a0a97b8900f37d4a71f1d75f52f56eeb</id>
<content type='text'>
Start using drm_gpu_scheduler.ready isntead.

v3:
Add helper function to run ring test and set
sched.ready flag status accordingly, clean explicit
sched.ready sets from the IP specific files.

v4: Add kerneldoc and rebase.

Signed-off-by: Andrey Grodzovsky &lt;andrey.grodzovsky@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add ring soft recovery v4</title>
<updated>2018-08-27T20:10:07Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-08-21T09:11:36Z</published>
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<id>urn:sha1:7876fa4f55fda4a57348832f4a668279ed2b2fc4</id>
<content type='text'>
Instead of hammering hard on the GPU try a soft recovery first.

v2: reorder code a bit
v3: increase timeout to 10ms, increment GPU reset counter
v4: squash in compile fix (Christian)

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Huang Rui &lt;ray.huang@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: remove ring lru handling</title>
<updated>2018-08-27T16:10:47Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-07-16T13:23:15Z</published>
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<id>urn:sha1:86275d090f0196d63245796aa0e3a12fa17e61a5</id>
<content type='text'>
Not needed any more.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: allow for more flexible priority handling</title>
<updated>2018-07-18T21:18:43Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-07-16T11:47:34Z</published>
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<id>urn:sha1:9d46f32bdd3e9d4bf435c5ae50f72fb475bf0620</id>
<content type='text'>
Allow to call amdgpu_ring_priority_get() after pushing the ring to the
scheduler.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: define and add extra dword for jpeg ring</title>
<updated>2018-06-15T17:20:37Z</updated>
<author>
<name>Boyuan Zhang</name>
<email>boyuan.zhang@amd.com</email>
</author>
<published>2018-06-01T16:30:17Z</published>
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<id>urn:sha1:c8c1a1d2ef040d2661fc9c7f0b32aec5b1058ae3</id>
<content type='text'>
Define extra dword for jpeg ring. Jpeg ring will allocate extra dword to store
the patch commands for fixing the known issue.

v2: dropping extra_dw for rings other than jpeg.

Signed-off-by: Boyuan Zhang &lt;boyuan.zhang@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/vg20:Restruct uvd.inst to support multiple instances</title>
<updated>2018-05-18T21:08:12Z</updated>
<author>
<name>James Zhu</name>
<email>James.Zhu@amd.com</email>
</author>
<published>2018-05-15T19:31:24Z</published>
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<id>urn:sha1:10dd74eac4dba963bfa97f5092040aa75ff742d6</id>
<content type='text'>
Vega20 has dual-UVD. Need add multiple instances support for uvd.
Restruct uvd.inst, using uvd.inst[0] to replace uvd.inst-&gt;.
Repurpose amdgpu_ring::me for instance index, and initialize to 0.
There are no any logical changes here.

Signed-off-by: James Zhu &lt;James.Zhu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add emit_reg_write_reg_wait ring callback</title>
<updated>2018-05-15T18:43:13Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2018-03-27T16:58:14Z</published>
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<id>urn:sha1:828536385ab0d25b5ddd7153347df04ea3a6961d</id>
<content type='text'>
This callback writes a value to a register and then reads
back another register and waits for a value in a single
operation.

Provide a helper function using two operations for engines
that don't support this opertion.

Reviewed-by: Huang Rui &lt;ray.huang@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: Mask rptr as well in ring debugfs</title>
<updated>2018-03-01T17:04:17Z</updated>
<author>
<name>Tom St Denis</name>
<email>tom.stdenis@amd.com</email>
</author>
<published>2018-03-01T14:39:57Z</published>
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<id>urn:sha1:9c5c71bbed4132a3a5f200064914db768c88302a</id>
<content type='text'>
The read/write pointers on sdma4 devices increment
beyond the ring size and should be masked.  Tested
on my Ryzen 2400G.

Signed-off-by: Tom St Denis &lt;tom.stdenis@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
