<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h, branch v4.15</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v4.15</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v4.15'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2017-10-19T19:27:19Z</updated>
<entry>
<title>drm/amdgpu: busywait KIQ register accessing (v4)</title>
<updated>2017-10-19T19:27:19Z</updated>
<author>
<name>pding</name>
<email>Pixel.Ding@amd.com</email>
</author>
<published>2017-10-13T07:38:35Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=43ca8efa46d9b1c4defa1b27c4dd1ef3866aaad9'/>
<id>urn:sha1:43ca8efa46d9b1c4defa1b27c4dd1ef3866aaad9</id>
<content type='text'>
Register accessing is performed when IRQ is disabled. Never sleep in
this function.

Known issue: dead sleep in many use cases of index/data registers.

v2:
 - wrap polling fence functions.
 - don't trigger IRQ for polling in case of wrongly fence signal.

v3:
 - handle wrap round gracefully.
 - add comments for polling function

v4:
 - don't return negative timeout confused with error code

Signed-off-by: pding &lt;Pixel.Ding@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add framework for HW specific priority settings v9</title>
<updated>2017-10-09T20:30:21Z</updated>
<author>
<name>Andres Rodriguez</name>
<email>andresx7@gmail.com</email>
</author>
<published>2017-02-20T22:53:19Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=b2ff0e8ac4ce1fb647ae40feb4cf26bc9301e0c9'/>
<id>urn:sha1:b2ff0e8ac4ce1fb647ae40feb4cf26bc9301e0c9</id>
<content type='text'>
Add an initial framework for changing the HW priorities of rings. The
framework allows requesting priority changes for the lifetime of an
amdgpu_job. After the job completes the priority will decay to the next
lowest priority for which a request is still valid.

A new ring function set_priority() can now be populated to take care of
the HW specific programming sequence for priority changes.

v2: set priority before emitting IB, and take a ref on amdgpu_job
v3: use AMD_SCHED_PRIORITY_* instead of AMDGPU_CTX_PRIORITY_*
v4: plug amdgpu_ring_restore_priority_cb into amdgpu_job_free_cb
v5: use atomic for tracking job priorities instead of last_job
v6: rename amdgpu_ring_priority_[get/put]() and align parameters
v7: replace spinlocks with mutexes for KIQ compatibility
v8: raise ring priority during cs_ioctl, instead of job_run
v9: priority_get() before push_job()

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Andres Rodriguez &lt;andresx7@gmail.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: map compute rings by least recently used pipe</title>
<updated>2017-09-28T20:03:22Z</updated>
<author>
<name>Andres Rodriguez</name>
<email>andresx7@gmail.com</email>
</author>
<published>2017-09-26T21:43:14Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=35161bbc135a748dd0a3c822030b3341cdefbd33'/>
<id>urn:sha1:35161bbc135a748dd0a3c822030b3341cdefbd33</id>
<content type='text'>
This patch provides a guarantee that the first n queues allocated by
an application will be on different pipes. Where n is the number of
pipes available from the hardware.

This helps avoid ring aliasing which can result in work executing in
time-sliced mode instead of truly parallel mode.

Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Andres Rodriguez &lt;andresx7@gmail.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fix amdgpu_ring_write_multiple</title>
<updated>2017-07-14T15:05:56Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2017-06-28T11:50:07Z</published>
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<id>urn:sha1:369421cbfabf0650b73571d7d1c026fc3830e74d</id>
<content type='text'>
Overwriting still used ring content has a low probability to cause
problems, not writing at all has 100% probability to cause problems.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Acked-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: move ring helpers to amdgpu_ring.h</title>
<updated>2017-07-14T15:05:56Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2017-06-28T11:43:48Z</published>
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<id>urn:sha1:e8110b1c9bdd3d76610a9783724233a570964d3c</id>
<content type='text'>
Keep them where they belong.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Acked-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Move compute vm bug logic to amdgpu_vm.c</title>
<updated>2017-06-01T20:00:20Z</updated>
<author>
<name>Alex Xie</name>
<email>AlexBin.Xie@amd.com</email>
</author>
<published>2017-06-01T13:42:59Z</published>
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<id>urn:sha1:e59c020598666ffc22c627910667e44ac2412304</id>
<content type='text'>
  In review, Christian would like to keep the logic
  inside amdgpu_vm.c with a cost of slightly slower.
  The loop is still optimized out with this patch.

v2: remove the if statement. Now it is not slower.

Signed-off-by: Alex Xie &lt;AlexBin.Xie@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koeng@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: guarantee bijective mapping of ring ids for LRU v3</title>
<updated>2017-05-31T20:49:03Z</updated>
<author>
<name>Andres Rodriguez</name>
<email>andresx7@gmail.com</email>
</author>
<published>2017-03-17T18:30:15Z</published>
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<id>urn:sha1:6065343a116fce16f7523ab10841efd942ce612d</id>
<content type='text'>
Depending on usage patterns, the current LRU policy may create a
non-injective mapping between userspace ring ids and kernel rings.

This behaviour is undesired as apps that attempt to fill all HW blocks
would be unable to reach some of them.

This change forces the LRU policy to create bijective mappings only.

v2: compress ring_blacklist
v3: simplify amdgpu_ring_is_blacklisted() logic

Signed-off-by: Andres Rodriguez &lt;andresx7@gmail.com&gt;
Reviewed-by: Nicolai Hähnle &lt;nicolai.haehnle@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: implement lru amdgpu_queue_mgr policy for compute v4</title>
<updated>2017-05-31T20:49:02Z</updated>
<author>
<name>Andres Rodriguez</name>
<email>andresx7@gmail.com</email>
</author>
<published>2017-03-06T21:27:55Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=795f2813e628bcf57a69f2dfe413360d14a1d7f4'/>
<id>urn:sha1:795f2813e628bcf57a69f2dfe413360d14a1d7f4</id>
<content type='text'>
Use an LRU policy to map usermode rings to HW compute queues.

Most compute clients use one queue, and usually the first queue
available. This results in poor pipe/queue work distribution when
multiple compute apps are running. In most cases pipe 0 queue 0 is
the only queue that gets used.

In order to better distribute work across multiple HW queues, we adopt
a policy to map the usermode ring ids to the LRU HW queue.

This fixes a large majority of multi-app compute workloads sharing the
same HW queue, even though 7 other queues are available.

v2: use ring-&gt;funcs-&gt;type instead of ring-&gt;hw_ip
v3: remove amdgpu_queue_mapper_funcs
v4: change ring_lru_list_lock to spinlock, grab only once in lru_get()

Signed-off-by: Andres Rodriguez &lt;andresx7@gmail.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Optimize a function called by every IB sheduling</title>
<updated>2017-05-31T18:16:38Z</updated>
<author>
<name>Alex Xie</name>
<email>AlexBin.Xie@amd.com</email>
</author>
<published>2017-05-30T21:10:16Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=dd684d313e280c3bad2ebb7b33e7688ab5409bc9'/>
<id>urn:sha1:dd684d313e280c3bad2ebb7b33e7688ab5409bc9</id>
<content type='text'>
  Move several if statements and a loop statment from
  run time to initialization time.

Signed-off-by: Alex Xie &lt;AlexBin.Xie@amd.com&gt;
Reviewed-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add vcn enc ring type and functions</title>
<updated>2017-05-24T21:41:41Z</updated>
<author>
<name>Leo Liu</name>
<email>leo.liu@amd.com</email>
</author>
<published>2017-02-21T15:36:15Z</published>
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<id>urn:sha1:8ace845ff0e8fc610686c0fa12ec05130fbf1f6b</id>
<content type='text'>
Add the ring function callbacks for the encode rings.

Signed-off-by: Leo Liu &lt;leo.liu@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
