<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h, branch v5.14</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.14</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.14'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2021-05-20T03:45:49Z</updated>
<entry>
<title>drm/amdgpu: Split amdgpu_device_fini into early and late</title>
<updated>2021-05-20T03:45:49Z</updated>
<author>
<name>Andrey Grodzovsky</name>
<email>andrey.grodzovsky@amd.com</email>
</author>
<published>2021-05-12T14:26:34Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=72c8c97b1522ce7ed1789a42fc9828784ebb5e23'/>
<id>urn:sha1:72c8c97b1522ce7ed1789a42fc9828784ebb5e23</id>
<content type='text'>
Some of the stuff in amdgpu_device_fini such as HW interrupts
disable and pending fences finilization must be done right away on
pci_remove while most of the stuff which relates to finilizing and
releasing driver data structures can be kept until
drm_driver.release hook is called, i.e. when the last device
reference is dropped.

v4: Change functions prefix early-&gt;hw and late-&gt;sw

Signed-off-by: Andrey Grodzovsky &lt;andrey.grodzovsky@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20210512142648.666476-3-andrey.grodzovsky@amd.com
</content>
</entry>
<entry>
<title>drm/amdgpu: add the sched_score to amdgpu_ring_init</title>
<updated>2021-04-09T20:44:56Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2021-02-02T12:05:49Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=c107171b8d3241d872807c04917e7e8fb70e8b71'/>
<id>urn:sha1:c107171b8d3241d872807c04917e7e8fb70e8b71</id>
<content type='text'>
Allow separate ring to share the same scheduler score.

No functional change.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-and-Tested-by: Leo Liu &lt;leo.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add wave limit functionality for gfx8,9</title>
<updated>2021-02-09T20:27:04Z</updated>
<author>
<name>Nirmoy Das</name>
<email>nirmoy.das@amd.com</email>
</author>
<published>2021-01-27T10:35:54Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=0a52a6cacca6030374fca7087e8556b382cca0e3'/>
<id>urn:sha1:0a52a6cacca6030374fca7087e8556b382cca0e3</id>
<content type='text'>
Wave limiting can be use to load balance high priority
compute jobs along with gfx jobs. When enabled, this will reserve
~75% of waves for compute jobs.

We do not need this from gfx10 onwards because &gt;=gfx10 has
asynchronous compute tunneling to replace wave limit requirement.

Signed-off-by: Nirmoy Das &lt;nirmoy.das@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: cleanup struct amdgpu_ring</title>
<updated>2021-02-09T20:26:41Z</updated>
<author>
<name>Nirmoy Das</name>
<email>nirmoy.das@amd.com</email>
</author>
<published>2021-02-01T14:02:30Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=ebdd2e9d1aef29a2eb7b797abe6d0e048ce00a7f'/>
<id>urn:sha1:ebdd2e9d1aef29a2eb7b797abe6d0e048ce00a7f</id>
<content type='text'>
This patch consist of below related changes:

1 Rename ring-&gt;priority to ring-&gt;hw_prio.
2 Assign correct hardware ring priority.
3 Remove ring-&gt;priority_mutex as ring priority remains unchanged
  after initialization.
4 Remove unused ring-&gt;num_jobs.

v3: remove ring-&gt;num_jobs.
v2: remove ring-&gt;priority_mutex.

Fixes: 33abcb1f5a17 ("drm/amdgpu: set compute queue priority at mqd_init")
Signed-off-by: Nirmoy Das &lt;nirmoy.das@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/scheduler: Scheduler priority fixes (v2)</title>
<updated>2020-08-18T22:20:17Z</updated>
<author>
<name>Luben Tuikov</name>
<email>luben.tuikov@amd.com</email>
</author>
<published>2020-08-11T23:59:58Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=e2d732fdb7a9e421720a644580cd6a9400f97f60'/>
<id>urn:sha1:e2d732fdb7a9e421720a644580cd6a9400f97f60</id>
<content type='text'>
Remove DRM_SCHED_PRIORITY_LOW, as it was used
in only one place.

Rename and separate by a line
DRM_SCHED_PRIORITY_MAX to DRM_SCHED_PRIORITY_COUNT
as it represents a (total) count of said
priorities and it is used as such in loops
throughout the code. (0-based indexing is the
the count number.)

Remove redundant word HIGH in priority names,
and rename *KERNEL* to *HIGH*, as it really
means that, high.

v2: Add back KERNEL and remove SW and HW,
    in lieu of a single HIGH between NORMAL and KERNEL.

Signed-off-by: Luben Tuikov &lt;luben.tuikov@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add the ring type definition of MES</title>
<updated>2020-07-01T05:59:07Z</updated>
<author>
<name>Jack Xiao</name>
<email>Jack.Xiao@amd.com</email>
</author>
<published>2020-04-09T18:16:40Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=cdca7979456359a8186459c677d1f4705ebbf72a'/>
<id>urn:sha1:cdca7979456359a8186459c677d1f4705ebbf72a</id>
<content type='text'>
Add a new ring type definition.

Signed-off-by: Jack Xiao &lt;Jack.Xiao@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add new ring callback to insert memory sync</title>
<updated>2020-05-18T15:24:21Z</updated>
<author>
<name>Andrey Grodzovsky</name>
<email>andrey.grodzovsky@amd.com</email>
</author>
<published>2020-03-24T20:37:01Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=22301177dbcb99eb1101ed5698c5b2239d024f8f'/>
<id>urn:sha1:22301177dbcb99eb1101ed5698c5b2239d024f8f</id>
<content type='text'>
Used to flush and invalidate various caches.

v2: Rename function hook

Signed-off-by: Andrey Grodzovsky &lt;andrey.grodzovsky@amd.com&gt;
Reviewed-by: Luben Tuikov &lt;luben.tuikov@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: cleanup IB pool handling a bit</title>
<updated>2020-04-28T20:20:30Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2020-04-01T09:18:21Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=9ecefb19c3a6626c27ea7ee72d431f22462e1d54'/>
<id>urn:sha1:9ecefb19c3a6626c27ea7ee72d431f22462e1d54</id>
<content type='text'>
Fix the coding style, move and rename the definitions to
better match what they are supposed to be doing.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Fix per-IB secure flag GFX hang</title>
<updated>2020-04-28T20:20:30Z</updated>
<author>
<name>Huang Rui</name>
<email>ray.huang@amd.com</email>
</author>
<published>2020-03-09T18:52:06Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=f77c9aff85caa9e9b0c2b6fc5be1fc2c76fe02b2'/>
<id>urn:sha1:f77c9aff85caa9e9b0c2b6fc5be1fc2c76fe02b2</id>
<content type='text'>
Since commit "Move to a per-IB secure flag (TMZ)",
we've been seeing hangs in GFX. We need to send
FRAME CONTROL stop/start back-to-back, every time
we flip the TMZ flag. That is, when we transition
from TMZ to non-TMZ we have to send a stop with
TMZ followed by a start with non-TMZ, and
similarly for transitioning from non-TMZ into TMZ.

This patch implements this, thus fixing the GFX
hang.

v1 -&gt; v2:
As suggested by Luben, and accept part of implemetation from this patch:
- Put "secure" closed to the loop and use optimization
- Change "secure" to bool again, and move "secure == -1" out of loop.
v3: Small fixes/optimizations.

Reported-and-Tested-by: Pierre-Eric Pelloux-Prayer &lt;pierre-eric.pelloux-prayer@amd.com&gt;
Signed-off-by: Huang Rui &lt;ray.huang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Luben Tuikov &lt;luben.tuikov@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Move to a per-IB secure flag (TMZ)</title>
<updated>2020-04-28T20:20:29Z</updated>
<author>
<name>Luben Tuikov</name>
<email>luben.tuikov@amd.com</email>
</author>
<published>2020-04-22T21:56:56Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=0bb5d5b03f78aeb5f87d47877eb15532875c64da'/>
<id>urn:sha1:0bb5d5b03f78aeb5f87d47877eb15532875c64da</id>
<content type='text'>
Move from a per-CS secure flag (TMZ) to a per-IB
secure flag.

Signed-off-by: Luben Tuikov &lt;luben.tuikov@amd.com&gt;
Reviewed-by: Huang Rui &lt;ray.huang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
