<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h, branch v5.15</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.15</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.15'/>
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<updated>2021-08-16T19:16:58Z</updated>
<entry>
<title>drm/amd/amdgpu embed hw_fence into amdgpu_job</title>
<updated>2021-08-16T19:16:58Z</updated>
<author>
<name>Jack Zhang</name>
<email>Jack.Zhang1@amd.com</email>
</author>
<published>2021-05-12T07:06:35Z</published>
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<id>urn:sha1:c530b02f39850a639b72d01ebbf7e5d745c60831</id>
<content type='text'>
Why: Previously hw fence is alloced separately with job.
It caused historical lifetime issues and corner cases.
The ideal situation is to take fence to manage both job
and fence's lifetime, and simplify the design of gpu-scheduler.

How:
We propose to embed hw_fence into amdgpu_job.
1. We cover the normal job submission by this method.
2. For ib_test, and submit without a parent job keep the
legacy way to create a hw fence separately.
v2:
use AMDGPU_FENCE_FLAG_EMBED_IN_JOB_BIT to show that the fence is
embedded in a job.
v3:
remove redundant variable ring in amdgpu_job
v4:
add tdr sequence support for this feature. Add a job_run_counter to
indicate whether this job is a resubmit job.
v5
add missing handling in amdgpu_fence_enable_signaling

Signed-off-by: Jingwen Chen &lt;Jingwen.Chen2@amd.com&gt;
Signed-off-by: Jack Zhang &lt;Jack.Zhang7@hotmail.com&gt;
Reviewed-by: Andrey Grodzovsky &lt;andrey.grodzovsky@amd.com&gt;
Reviewed by: Monk Liu &lt;monk.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: avoid over-handle of fence driver fini in s3 test (v2)</title>
<updated>2021-08-06T01:17:58Z</updated>
<author>
<name>Guchun Chen</name>
<email>guchun.chen@amd.com</email>
</author>
<published>2021-07-29T10:35:13Z</published>
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<id>urn:sha1:067f44c8b4590c3f24d21a037578a478590f2175</id>
<content type='text'>
In amdgpu_fence_driver_hw_fini, no need to call drm_sched_fini to stop
scheduler in s3 test, otherwise, fence related failure will arrive
after resume. To fix this and for a better clean up, move drm_sched_fini
from fence_hw_fini to fence_sw_fini, as it's part of driver shutdown, and
should never be called in hw_fini.

v2: rename amdgpu_fence_driver_init to amdgpu_fence_driver_sw_init,
to keep sw_init and sw_fini paired.

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1668
Fixes: 8d35a2596164c1 ("drm/amdgpu: adjust fence driver enable sequence")
Suggested-by: Christian König &lt;christian.koenig@amd.com&gt;
Tested-by: Mike Lothian &lt;mike@fireburn.co.uk&gt;
Signed-off-by: Guchun Chen &lt;guchun.chen@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: adjust fence driver enable sequence</title>
<updated>2021-07-29T02:15:44Z</updated>
<author>
<name>Likun Gao</name>
<email>Likun.Gao@amd.com</email>
</author>
<published>2021-07-26T09:17:52Z</published>
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<id>urn:sha1:8d35a2596164c1c9d34d4656fd42b445cd1e247f</id>
<content type='text'>
Fence driver was enabled per ring when sw init on per IP block before.
Change to enable all the fence driver at the same time after
amdgpu_device_ip_init finished.
Rename some function related to fence to make it reasonable for read.

Signed-off-by: Likun Gao &lt;Likun.Gao@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Split amdgpu_device_fini into early and late</title>
<updated>2021-05-20T03:45:49Z</updated>
<author>
<name>Andrey Grodzovsky</name>
<email>andrey.grodzovsky@amd.com</email>
</author>
<published>2021-05-12T14:26:34Z</published>
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<id>urn:sha1:72c8c97b1522ce7ed1789a42fc9828784ebb5e23</id>
<content type='text'>
Some of the stuff in amdgpu_device_fini such as HW interrupts
disable and pending fences finilization must be done right away on
pci_remove while most of the stuff which relates to finilizing and
releasing driver data structures can be kept until
drm_driver.release hook is called, i.e. when the last device
reference is dropped.

v4: Change functions prefix early-&gt;hw and late-&gt;sw

Signed-off-by: Andrey Grodzovsky &lt;andrey.grodzovsky@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20210512142648.666476-3-andrey.grodzovsky@amd.com
</content>
</entry>
<entry>
<title>drm/amdgpu: add the sched_score to amdgpu_ring_init</title>
<updated>2021-04-09T20:44:56Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2021-02-02T12:05:49Z</published>
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<id>urn:sha1:c107171b8d3241d872807c04917e7e8fb70e8b71</id>
<content type='text'>
Allow separate ring to share the same scheduler score.

No functional change.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-and-Tested-by: Leo Liu &lt;leo.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add wave limit functionality for gfx8,9</title>
<updated>2021-02-09T20:27:04Z</updated>
<author>
<name>Nirmoy Das</name>
<email>nirmoy.das@amd.com</email>
</author>
<published>2021-01-27T10:35:54Z</published>
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<id>urn:sha1:0a52a6cacca6030374fca7087e8556b382cca0e3</id>
<content type='text'>
Wave limiting can be use to load balance high priority
compute jobs along with gfx jobs. When enabled, this will reserve
~75% of waves for compute jobs.

We do not need this from gfx10 onwards because &gt;=gfx10 has
asynchronous compute tunneling to replace wave limit requirement.

Signed-off-by: Nirmoy Das &lt;nirmoy.das@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: cleanup struct amdgpu_ring</title>
<updated>2021-02-09T20:26:41Z</updated>
<author>
<name>Nirmoy Das</name>
<email>nirmoy.das@amd.com</email>
</author>
<published>2021-02-01T14:02:30Z</published>
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<id>urn:sha1:ebdd2e9d1aef29a2eb7b797abe6d0e048ce00a7f</id>
<content type='text'>
This patch consist of below related changes:

1 Rename ring-&gt;priority to ring-&gt;hw_prio.
2 Assign correct hardware ring priority.
3 Remove ring-&gt;priority_mutex as ring priority remains unchanged
  after initialization.
4 Remove unused ring-&gt;num_jobs.

v3: remove ring-&gt;num_jobs.
v2: remove ring-&gt;priority_mutex.

Fixes: 33abcb1f5a17 ("drm/amdgpu: set compute queue priority at mqd_init")
Signed-off-by: Nirmoy Das &lt;nirmoy.das@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/scheduler: Scheduler priority fixes (v2)</title>
<updated>2020-08-18T22:20:17Z</updated>
<author>
<name>Luben Tuikov</name>
<email>luben.tuikov@amd.com</email>
</author>
<published>2020-08-11T23:59:58Z</published>
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<id>urn:sha1:e2d732fdb7a9e421720a644580cd6a9400f97f60</id>
<content type='text'>
Remove DRM_SCHED_PRIORITY_LOW, as it was used
in only one place.

Rename and separate by a line
DRM_SCHED_PRIORITY_MAX to DRM_SCHED_PRIORITY_COUNT
as it represents a (total) count of said
priorities and it is used as such in loops
throughout the code. (0-based indexing is the
the count number.)

Remove redundant word HIGH in priority names,
and rename *KERNEL* to *HIGH*, as it really
means that, high.

v2: Add back KERNEL and remove SW and HW,
    in lieu of a single HIGH between NORMAL and KERNEL.

Signed-off-by: Luben Tuikov &lt;luben.tuikov@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add the ring type definition of MES</title>
<updated>2020-07-01T05:59:07Z</updated>
<author>
<name>Jack Xiao</name>
<email>Jack.Xiao@amd.com</email>
</author>
<published>2020-04-09T18:16:40Z</published>
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<id>urn:sha1:cdca7979456359a8186459c677d1f4705ebbf72a</id>
<content type='text'>
Add a new ring type definition.

Signed-off-by: Jack Xiao &lt;Jack.Xiao@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add new ring callback to insert memory sync</title>
<updated>2020-05-18T15:24:21Z</updated>
<author>
<name>Andrey Grodzovsky</name>
<email>andrey.grodzovsky@amd.com</email>
</author>
<published>2020-03-24T20:37:01Z</published>
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<id>urn:sha1:22301177dbcb99eb1101ed5698c5b2239d024f8f</id>
<content type='text'>
Used to flush and invalidate various caches.

v2: Rename function hook

Signed-off-by: Andrey Grodzovsky &lt;andrey.grodzovsky@amd.com&gt;
Reviewed-by: Luben Tuikov &lt;luben.tuikov@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
