<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h, branch v5.8</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.8</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.8'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2020-05-18T15:24:21Z</updated>
<entry>
<title>drm/amdgpu: Add new ring callback to insert memory sync</title>
<updated>2020-05-18T15:24:21Z</updated>
<author>
<name>Andrey Grodzovsky</name>
<email>andrey.grodzovsky@amd.com</email>
</author>
<published>2020-03-24T20:37:01Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=22301177dbcb99eb1101ed5698c5b2239d024f8f'/>
<id>urn:sha1:22301177dbcb99eb1101ed5698c5b2239d024f8f</id>
<content type='text'>
Used to flush and invalidate various caches.

v2: Rename function hook

Signed-off-by: Andrey Grodzovsky &lt;andrey.grodzovsky@amd.com&gt;
Reviewed-by: Luben Tuikov &lt;luben.tuikov@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: cleanup IB pool handling a bit</title>
<updated>2020-04-28T20:20:30Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2020-04-01T09:18:21Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=9ecefb19c3a6626c27ea7ee72d431f22462e1d54'/>
<id>urn:sha1:9ecefb19c3a6626c27ea7ee72d431f22462e1d54</id>
<content type='text'>
Fix the coding style, move and rename the definitions to
better match what they are supposed to be doing.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Fix per-IB secure flag GFX hang</title>
<updated>2020-04-28T20:20:30Z</updated>
<author>
<name>Huang Rui</name>
<email>ray.huang@amd.com</email>
</author>
<published>2020-03-09T18:52:06Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=f77c9aff85caa9e9b0c2b6fc5be1fc2c76fe02b2'/>
<id>urn:sha1:f77c9aff85caa9e9b0c2b6fc5be1fc2c76fe02b2</id>
<content type='text'>
Since commit "Move to a per-IB secure flag (TMZ)",
we've been seeing hangs in GFX. We need to send
FRAME CONTROL stop/start back-to-back, every time
we flip the TMZ flag. That is, when we transition
from TMZ to non-TMZ we have to send a stop with
TMZ followed by a start with non-TMZ, and
similarly for transitioning from non-TMZ into TMZ.

This patch implements this, thus fixing the GFX
hang.

v1 -&gt; v2:
As suggested by Luben, and accept part of implemetation from this patch:
- Put "secure" closed to the loop and use optimization
- Change "secure" to bool again, and move "secure == -1" out of loop.
v3: Small fixes/optimizations.

Reported-and-Tested-by: Pierre-Eric Pelloux-Prayer &lt;pierre-eric.pelloux-prayer@amd.com&gt;
Signed-off-by: Huang Rui &lt;ray.huang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Luben Tuikov &lt;luben.tuikov@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Move to a per-IB secure flag (TMZ)</title>
<updated>2020-04-28T20:20:29Z</updated>
<author>
<name>Luben Tuikov</name>
<email>luben.tuikov@amd.com</email>
</author>
<published>2020-04-22T21:56:56Z</published>
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<id>urn:sha1:0bb5d5b03f78aeb5f87d47877eb15532875c64da</id>
<content type='text'>
Move from a per-CS secure flag (TMZ) to a per-IB
secure flag.

Signed-off-by: Luben Tuikov &lt;luben.tuikov@amd.com&gt;
Reviewed-by: Huang Rui &lt;ray.huang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: expand the context control interface with trust flag</title>
<updated>2020-04-28T20:20:28Z</updated>
<author>
<name>Huang Rui</name>
<email>ray.huang@amd.com</email>
</author>
<published>2020-04-22T21:49:17Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=8350361d2d75882573c7d1af228d7827666e6929'/>
<id>urn:sha1:8350361d2d75882573c7d1af228d7827666e6929</id>
<content type='text'>
This patch expands the context control function to support trusted flag while we
want to set command buffer in trusted mode.

Signed-off-by: Huang Rui &lt;ray.huang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: expand the emit tmz interface with trusted flag</title>
<updated>2020-04-28T20:20:28Z</updated>
<author>
<name>Huang Rui</name>
<email>ray.huang@amd.com</email>
</author>
<published>2020-03-09T17:53:37Z</published>
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<id>urn:sha1:155748c912e7063dfcf0cd071e289f4aff152672</id>
<content type='text'>
This patch expands the emit_tmz function to support trusted flag while we want
to set command buffer in trusted mode.

Signed-off-by: Huang Rui &lt;ray.huang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: protect ring overrun</title>
<updated>2020-04-24T15:42:11Z</updated>
<author>
<name>Yintian Tao</name>
<email>yttao@amd.com</email>
</author>
<published>2020-04-23T04:05:54Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=04e4e2e9558326316cf3e32d46cca83cc3861ef0'/>
<id>urn:sha1:04e4e2e9558326316cf3e32d46cca83cc3861ef0</id>
<content type='text'>
Wait for the oldest sequence on the ring
to be signaled in order to make sure there
will be no command overrun.

v2: fix coding stype and remove abs operation
v3: remove the initialization of variable r

Signed-off-by: Yintian Tao &lt;yttao@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: request reg_val_offs each kiq read reg</title>
<updated>2020-04-23T19:06:41Z</updated>
<author>
<name>Yintian Tao</name>
<email>yttao@amd.com</email>
</author>
<published>2020-04-22T11:58:22Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=5420819401cc7048a373d99407a8bb2cca7861c9'/>
<id>urn:sha1:5420819401cc7048a373d99407a8bb2cca7861c9</id>
<content type='text'>
According to the current kiq read register method,
there will be race condition when using KIQ to read
register if multiple clients want to read at same time
just like the expample below:
1. client-A start to read REG-0 throguh KIQ
2. client-A poll the seqno-0
3. client-B start to read REG-1 through KIQ
4. client-B poll the seqno-1
5. the kiq complete these two read operation
6. client-A to read the register at the wb buffer and
   get REG-1 value

Therefore, use amdgpu_device_wb_get() to request reg_val_offs
for each kiq read register.

v2: fix the error remove
v3: fix the print typo
v4: remove unused variables

Signed-off-by: Yintian Tao &lt;yttao@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/ring: add no_scheduler flag</title>
<updated>2020-04-13T16:02:19Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2020-04-09T19:56:05Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=cb3d1085019da94cf2b7d721600b4e5df93b4ef8'/>
<id>urn:sha1:cb3d1085019da94cf2b7d721600b4e5df93b4ef8</id>
<content type='text'>
This allows IPs to flag whether a specific ring requires
a GPU scheduler or not.  E.g., sometimes instances of an
IP are asymmetric and have different capabilities.

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: rework sched_list generation</title>
<updated>2020-04-09T14:43:14Z</updated>
<author>
<name>Nirmoy Das</name>
<email>nirmoy.das@amd.com</email>
</author>
<published>2020-04-01T09:46:57Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=1c6d567bdf73a207f51ef2e5745854ba7daa22c7'/>
<id>urn:sha1:1c6d567bdf73a207f51ef2e5745854ba7daa22c7</id>
<content type='text'>
Generate HW IP's sched_list in amdgpu_ring_init() instead of
amdgpu_ctx.c. This makes amdgpu_ctx_init_compute_sched(),
ring.has_high_prio and amdgpu_ctx_init_sched() unnecessary.
This patch also stores sched_list for all HW IPs in one big
array in struct amdgpu_device which makes amdgpu_ctx_init_entity()
much more leaner.

v2:
fix a coding style issue
do not use drm hw_ip const to populate amdgpu_ring_type enum

v3:
remove ctx reference and move sched array and num_sched to a struct
use num_scheds to detect uninitialized scheduler list

v4:
use array_index_nospec for user space controlled variables
fix possible checkpatch.pl warnings

Signed-off-by: Nirmoy Das &lt;nirmoy.das@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
