<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h, branch v6.16</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v6.16</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v6.16'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2025-06-18T17:15:26Z</updated>
<entry>
<title>drm/amdgpu: switch job hw_fence to amdgpu_fence</title>
<updated>2025-06-18T17:15:26Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2025-06-02T15:31:52Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=ebe43542702c3d15d1a1d95e8e13b1b54076f05a'/>
<id>urn:sha1:ebe43542702c3d15d1a1d95e8e13b1b54076f05a</id>
<content type='text'>
Use the amdgpu fence container so we can store additional
data in the fence.  This also fixes the start_time handling
for MCBP since we were casting the fence to an amdgpu_fence
and it wasn't.

Fixes: 3f4c175d62d8 ("drm/amdgpu: MCBP based on DRM scheduler (v9)")
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
(cherry picked from commit bf1cd14f9e2e1fdf981eed273ddd595863f5288c)
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu: Add documentation to some parts of the AMDGPU ring and wb</title>
<updated>2025-05-07T21:41:35Z</updated>
<author>
<name>Rodrigo Siqueira</name>
<email>siqueira@igalia.com</email>
</author>
<published>2025-05-03T20:38:42Z</published>
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<id>urn:sha1:c8305c6327b4c2ef812a6eca544d8e7c5e8a0b30</id>
<content type='text'>
Add some random documentation associated with the ring buffer
manipulations and writeback.

Signed-off-by: Rodrigo Siqueira &lt;siqueira@igalia.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add ring flag for no user submissions</title>
<updated>2025-04-08T20:48:22Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2025-02-18T18:06:19Z</published>
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<id>urn:sha1:4310acd4464bc6aed0d211d94b1d343ea3cb62f8</id>
<content type='text'>
This would be set by IPs which only accept submissions
from the kernel, not userspace, such as when kernel
queues are disabled. Don't expose the rings to userspace
and reject any submissions in the CS IOCTL.

v2: fix error code (Alex)

Reviewed-by: Sunil Khatri&lt;sunil.khatri@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: remove is_mes_queue flag</title>
<updated>2025-04-08T20:48:21Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2025-03-12T17:47:33Z</published>
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<id>urn:sha1:4220d2c7c41b8ea3fd154dc5678b05575653cba0</id>
<content type='text'>
This was leftover from MES bring up when we had MES
user queues in the kernel.  It's no longer used so
remove it.

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: Increase max rings to enable SDMA page ring</title>
<updated>2025-03-21T16:16:35Z</updated>
<author>
<name>Jesse.zhang@amd.com</name>
<email>Jesse.zhang@amd.com</email>
</author>
<published>2025-02-28T08:18:32Z</published>
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<id>urn:sha1:ea6dd40cafdbf5f735b3d84dd61df93d107aff38</id>
<content type='text'>
Increase the maximum number of rings supported by the AMDGPU driver from 133 to 149.
This change is necessary to enable support for the SDMA page ring.

Signed-off-by: Jesse Zhang &lt;jesse.zhang@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: increase AMDGPU_MAX_RINGS</title>
<updated>2025-02-25T16:45:13Z</updated>
<author>
<name>Tao Zhou</name>
<email>tao.zhou1@amd.com</email>
</author>
<published>2025-02-25T11:18:12Z</published>
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<id>urn:sha1:dab993bf151359e4e4d045c5469f34333e88e359</id>
<content type='text'>
Increase it since a cper ring is introduced.

Signed-off-by: Tao Zhou &lt;tao.zhou1@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Introduce cached_rptr and is_guilty callback in amdgpu_ring</title>
<updated>2025-02-25T16:43:59Z</updated>
<author>
<name>Jesse.zhang@amd.com</name>
<email>Jesse.zhang@amd.com</email>
</author>
<published>2025-02-13T02:30:07Z</published>
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<id>urn:sha1:4d3c4f4f7f22670ae7163b5f9bd6cfea28c2efc6</id>
<content type='text'>
This patch introduces the following changes:
- Add `cached_rptr` to the `amdgpu_ring` structure to store the read pointer before a reset.
- Add `is_guilty` callback to the `amdgpu_ring_funcs` structure to check if a ring is guilty of causing a timeout.

Suggested-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Jesse Zhang &lt;jesse.zhang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add RAS CPER ring buffer</title>
<updated>2025-02-17T19:09:29Z</updated>
<author>
<name>Tao Zhou</name>
<email>tao.zhou1@amd.com</email>
</author>
<published>2025-01-22T08:55:51Z</published>
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<id>urn:sha1:4d614ce8ffd757e4c7944bf9b5598b4a250a8a61</id>
<content type='text'>
And initialize it, this is a pure software ring to store RAS CPER data.

v2: change ring size to 0x100000
v2: update the initialization of count_dw of cper ring, it's dword
variable
v3: skip VM inv eng for cper
v3: init/fini when aca enabled

Signed-off-by: Tao Zhou &lt;tao.zhou1@amd.com&gt;
Signed-off-by: Xiang Liu &lt;xiang.liu@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: increase amdgpu max rings limit</title>
<updated>2025-02-13T02:02:54Z</updated>
<author>
<name>Sathishkumar S</name>
<email>sathishkumar.sundararaju@amd.com</email>
</author>
<published>2025-01-10T02:18:54Z</published>
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<id>urn:sha1:8064ca6e93e6361563b0de60204a51e4e12f932b</id>
<content type='text'>
increase max rings to 132 to support all JPEG5_0_1 cores, else
ring_init fails due to ring count exceeding maximum limit.

Signed-off-by: Sathishkumar S &lt;sathishkumar.sundararaju@amd.com&gt;
Reviewed-by: Leo Liu &lt;leo.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: drop the amdgpu_device argument from amdgpu_ib_free</title>
<updated>2024-12-18T17:17:32Z</updated>
<author>
<name>Pierre-Eric Pelloux-Prayer</name>
<email>pierre-eric.pelloux-prayer@amd.com</email>
</author>
<published>2024-12-06T12:16:14Z</published>
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<id>urn:sha1:0014952b1754b0dba3ea87d2d3b9784fdcec9f95</id>
<content type='text'>
It's unused.

Signed-off-by: Pierre-Eric Pelloux-Prayer &lt;pierre-eric.pelloux-prayer@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
