linux/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h, branch v6.3

amd/amdgpu: remove test ib on hw ring

2023-02-09T03:33:31Z

test ib function is not necessary on hw ring, so remove it. v2: squash in NULL check fix Signed-off-by: JesseZhang Acked-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: MCBP based on DRM scheduler (v9)

2022-12-02T15:04:51Z

Trigger Mid-Command Buffer Preemption according to the priority of the software rings and the hw fence signalling condition. The muxer saves the locations of the indirect buffer frames from the software ring together with the fence sequence number in its fifo queue, and pops out those records when the fences are signalled. The locations are used to resubmit packages in preemption scenarios by coping the chunks from the software ring. v2: Update comment style. v3: Fix conflict caused by previous modifications. v4: Remove unnecessary prints. v5: Fix corner cases for resubmission cases. v6: Refactor functions for resubmission, calling fence_process in irq handler. v7: Solve conflict for removing amdgpu_sw_ring.c. v8: Add time threshold to judge if preemption request is needed. v9: Correct comment spelling. Set fence emit timestamp before rsu assignment. Cc: Christian Koenig Cc: Luben Tuikov Cc: Andrey Grodzovsky Cc: Michel Dänzer Signed-off-by: Jiadong.Zhu Acked-by: Luben Tuikov Acked-by: Huang Rui Acked-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: Modify unmap_queue format for gfx9 (v6)

2022-12-02T15:04:45Z

1. Modify the unmap_queue package on gfx9. Add trailing fence to track the preemption done. 2. Modify emit_ce_meta emit_de_meta functions for the resumed ibs. v2: Restyle code not to use ternary operator. v3: Modify code format. v4: Enable Mid-Command Buffer Preemption for gfx9 by default. v5: Optimize the flag bit set for emit_fence. v6: Modify log message for preemption timeout. Cc: Christian Koenig Cc: Michel Dänzer Cc: Luben Tuikov Signed-off-by: Jiadong.Zhu Acked-by: Christian König Acked-by: Huang Rui Signed-off-by: Alex Deucher

drm/amdgpu: Add software ring callbacks for gfx9 (v8)

2022-12-02T15:04:37Z

Set ring functions with software ring callbacks on gfx9. The software ring could be tested by debugfs_test_ib case. v2: Set sw_ring 2 to enable software ring by default. v3: Remove the parameter for software ring enablement. v4: Use amdgpu_ring_init/fini for software rings. v5: Update for code format. Fix conflict. v6: Remove unnecessary checks and enable software ring on gfx9 by default. v7: Use static array for software ring names and priorities. v8: Stop creating software rings if no gfx ring existed. Cc: Christian Koenig Cc: Luben Tuikov Cc: Andrey Grodzovsky Cc: Michel Dänzer Cc: Likun Gao Signed-off-by: Jiadong.Zhu Acked-by: Luben Tuikov Acked-by: Huang Rui Acked-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: Introduce gfx software ring (v9)

2022-12-02T15:04:27Z

The software ring is created to support priority context while there is only one hardware queue for gfx. Every software ring has its fence driver and could be used as an ordinary ring for the GPU scheduler. Multiple software rings are bound to a real ring with the ring muxer. The packages committed on the software ring are copied to the real ring. v2: Use array to store software ring entry. v3: Remove unnecessary prints. v4: Remove amdgpu_ring_sw_init/fini functions, using gtt for sw ring buffer for later dma copy optimization. v5: Allocate ring entry dynamically in the muxer. v6: Update comments for the ring muxer. v7: Modify for function naming. v8: Combine software ring functions into amdgpu_ring_mux.c v9: Use kernel-doc comment on the get_rptr function. Cc: Christian Koenig Cc: Luben Tuikov Cc: Andrey Grodzovsky Cc: Michel Dänzer Signed-off-by: Jiadong.Zhu Acked-by: Huang Rui Acked-by: Luben Tuikov Acked-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: Prevent race between late signaled fences and GPU reset.

2022-06-28T15:24:24Z

Problem: After we start handling timed out jobs we assume there fences won't be signaled but we cannot be sure and sometimes they fire late. We need to prevent concurrent accesses to fence array from amdgpu_fence_driver_clear_job_fences during GPU reset and amdgpu_fence_process from a late EOP interrupt. Fix: Before accessing fence array in GPU disable EOP interrupt and flush all pending interrupt handlers for amdgpu device's interrupt line. v2: Switch from irq_get/put to full enable/disable_irq for amdgpu Signed-off-by: Andrey Grodzovsky Acked-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: define ring structure to access rptr/wptr/fence

2022-05-04T14:03:23Z

Define ring structure to access the cpu/gpu address of rptr/wptr/fence instead of dynamic calculation. Signed-off-by: Jack Xiao Acked-by: Christian König Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher

drm/amdgpu: add mes ctx data in amdgpu_ring

2022-05-04T14:03:20Z

Add mes context data structure in amdgpu_ring. Signed-off-by: Jack Xiao Acked-by: Christian König Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher

drm/amdgpu: add the per-context meta data v3

2022-05-04T14:03:17Z

The per-context meta data is a per-context data structure associated with a mes-managed hardware ring, which includes MCBP CSA, ring buffer and etc. v2: fix typo v3: a. use structure instead of typedef b. move amdgpu_mes_ctx_get_offs_* to amdgpu_ring.h c. use __aligned to make alignement Signed-off-by: Jack Xiao Acked-by: Christian König Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher

drm/amdgpu: add helper function to initialize mqd from ring v4

2022-05-04T14:03:14Z

Add the helper function to initialize mqd from ring configuration. v2: use if/else pair instead of ?/: pair v3: use simpler way to judge hqd_active v4: fix parameters to amdgpu_gfx_is_high_priority_compute_queue Signed-off-by: Jack Xiao Acked-by: Christian König Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher