<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c, branch v6.0</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v6.0</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v6.0'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2022-07-25T13:31:04Z</updated>
<entry>
<title>drm/amd/amdgpu: add TAP_DELAYS upload support for gfx10</title>
<updated>2022-07-25T13:31:04Z</updated>
<author>
<name>Chengming Gui</name>
<email>Jack.Gui@amd.com</email>
</author>
<published>2022-07-15T05:12:14Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=2207efdd8388bd300a0051b1775705d890abd306'/>
<id>urn:sha1:2207efdd8388bd300a0051b1775705d890abd306</id>
<content type='text'>
Support {GLOBAL/SE0/SE1/SE2/SE3}_TAP_DELAYS uploading.

v2: upload TAP_DELAYS before RLC autoload was triggered. (Hawking)

Signed-off-by: Chengming Gui &lt;Jack.Gui@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: simplify amdgpu_ucode_get_load_type()</title>
<updated>2022-06-08T15:40:37Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2022-05-24T13:57:49Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=c4d7738c9efc81a4f0364da1e673ab1b1cf91735'/>
<id>urn:sha1:c4d7738c9efc81a4f0364da1e673ab1b1cf91735</id>
<content type='text'>
This is the same as the default case, so drop the extra
logic.

Reviewed-by: Guchun Chen &lt;guchun.chen@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: support imu for gfx11</title>
<updated>2022-05-04T14:43:54Z</updated>
<author>
<name>Likun Gao</name>
<email>Likun.Gao@amd.com</email>
</author>
<published>2022-04-13T18:28:02Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=289bcffb9d76f575995113dd48c09de7f2deb1d1'/>
<id>urn:sha1:289bcffb9d76f575995113dd48c09de7f2deb1d1</id>
<content type='text'>
Add support to initialize imu for gfx v11.
IMU is a new power management block for
gfx which manages gfx power.

Signed-off-by: Likun Gao &lt;Likun.Gao@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: support RS64 CP fw front door load</title>
<updated>2022-05-04T14:43:54Z</updated>
<author>
<name>Likun Gao</name>
<email>Likun.Gao@amd.com</email>
</author>
<published>2022-04-12T21:00:11Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=14ab29241817582e1b92c29ccd738354b2d3241b'/>
<id>urn:sha1:14ab29241817582e1b92c29ccd738354b2d3241b</id>
<content type='text'>
Support to load RS64 CP firmware front door load.

Signed-off-by: Likun Gao &lt;Likun.Gao@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: renovate sdma fw struct</title>
<updated>2022-05-04T14:43:54Z</updated>
<author>
<name>Likun Gao</name>
<email>Likun.Gao@amd.com</email>
</author>
<published>2021-03-12T09:27:44Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=8e070831d3f814013796a32d1588447592cd589f'/>
<id>urn:sha1:8e070831d3f814013796a32d1588447592cd589f</id>
<content type='text'>
Add sdma firmware struct version 2 to support new SDMA v6 and forward
firmware version.

v2: squash in fix

Signed-off-by: Likun Gao &lt;Likun.Gao@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fix the fw size for sdma</title>
<updated>2022-05-04T14:43:54Z</updated>
<author>
<name>Likun Gao</name>
<email>Likun.Gao@amd.com</email>
</author>
<published>2022-04-12T20:57:45Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=aca670e41f9fe52176040553f174d517cbd69da9'/>
<id>urn:sha1:aca670e41f9fe52176040553f174d517cbd69da9</id>
<content type='text'>
For SDMA, if use the total size of SDMA TH0 and TH1 to allocate fw BO
may result to the ucode data overflow when copy ucode to BO as the PAGE
alignment.
IMU have the same issue.
Fix the above issue by alignment the fw size per fw ID.

Signed-off-by: Likun Gao &lt;Likun.Gao@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/gfx: refine fw hdr check fuction</title>
<updated>2022-05-04T14:43:53Z</updated>
<author>
<name>Likun Gao</name>
<email>Likun.Gao@amd.com</email>
</author>
<published>2021-05-31T06:16:56Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=7edda6749fb76ce84d7c0b2a9858be384eeecbf7'/>
<id>urn:sha1:7edda6749fb76ce84d7c0b2a9858be384eeecbf7</id>
<content type='text'>
The return value of function amdgpu_ucode_hdr_version
doesn't make sense, so change it to return true when
fw header version is match with passed in parameters.

Signed-off-by: Wenhui Sheng &lt;Wenhui.Sheng@amd.com&gt;
Signed-off-by: Likun Gao &lt;Likun.Gao@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: extend the show ucode name function</title>
<updated>2022-05-04T14:43:53Z</updated>
<author>
<name>Likun Gao</name>
<email>Likun.Gao@amd.com</email>
</author>
<published>2021-09-07T03:38:41Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=619c94c3b5494a1c0654fde415083a589d3f0048'/>
<id>urn:sha1:619c94c3b5494a1c0654fde415083a589d3f0048</id>
<content type='text'>
Extend amdgpu_ucode_name function to show SDMA TH0, TH1, IMU, RLCP, RLCV
and MES related ucode name via ucode id.

Signed-off-by: Likun Gao &lt;Likun.Gao@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: support IMU front door load</title>
<updated>2022-05-04T14:43:53Z</updated>
<author>
<name>Likun Gao</name>
<email>Likun.Gao@amd.com</email>
</author>
<published>2022-04-05T17:42:51Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=a32fa029218f17f48af8bb56e8f618befc650671'/>
<id>urn:sha1:a32fa029218f17f48af8bb56e8f618befc650671</id>
<content type='text'>
Support for front door to load IMU firmware.

Signed-off-by: Likun Gao &lt;Likun.Gao@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: support for new SDMA front door load</title>
<updated>2022-05-04T14:43:53Z</updated>
<author>
<name>Likun Gao</name>
<email>Likun.Gao@amd.com</email>
</author>
<published>2021-09-01T07:25:51Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=6777c8cfcace139822f645c59102d556c541d6d4'/>
<id>urn:sha1:6777c8cfcace139822f645c59102d556c541d6d4</id>
<content type='text'>
Support for SDMA v6_0 ucode front door load.

Signed-off-by: Likun Gao &lt;Likun.Gao@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
