<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h, branch v5.4</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.4</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.4'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2019-08-02T15:30:39Z</updated>
<entry>
<title>drm/amdgpu: extend PSP FW loading support to 8 SDMA instances</title>
<updated>2019-08-02T15:30:39Z</updated>
<author>
<name>John Clements</name>
<email>John.Clements@amd.com</email>
</author>
<published>2019-08-01T09:59:55Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=b86f8d8b2bc07b0f6802e9c6b481049a63f4a637'/>
<id>urn:sha1:b86f8d8b2bc07b0f6802e9c6b481049a63f4a637</id>
<content type='text'>
Arcturus has 8 instances of SDMA.  Update host to PSP interface
to handle it.

Signed-off-by: John Clements &lt;john.clements@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add PSP KDB loading support for Arcturus</title>
<updated>2019-08-02T15:30:39Z</updated>
<author>
<name>John Clements</name>
<email>John.Clements@amd.com</email>
</author>
<published>2019-07-22T10:06:58Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=dc0d962297af444fa45ecea077e4ae53d7518719'/>
<id>urn:sha1:dc0d962297af444fa45ecea077e4ae53d7518719</id>
<content type='text'>
Add support for the arcturus specific psp metadata to the
amdgpu firmware and properly parse it when loading it.

Signed-off-by: John Clements &lt;john.clements@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/: add ucodeID for 2nd vcn instance</title>
<updated>2019-07-18T19:18:05Z</updated>
<author>
<name>James Zhu</name>
<email>James.Zhu@amd.com</email>
</author>
<published>2019-06-04T18:44:33Z</published>
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<id>urn:sha1:a07d163c90bf7d649998fb43ac9eb9a01764d662</id>
<content type='text'>
add ucodeID for 2nd vcn instance

Signed-off-by: James Zhu &lt;James.Zhu@amd.com&gt;
Reviewed-by: Leo Liu &lt;leo.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: support key database loading for navi10</title>
<updated>2019-07-12T13:00:10Z</updated>
<author>
<name>Hawking Zhang</name>
<email>Hawking.Zhang@amd.com</email>
</author>
<published>2019-07-10T16:13:54Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=4298935924a9057f2424636d1d29ae7caef4764a'/>
<id>urn:sha1:4298935924a9057f2424636d1d29ae7caef4764a</id>
<content type='text'>
Starting from navi10, driver should send Key Database Load command
to bootloader before loading sys_drv and sos

Signed-off-by: John Clements &lt;John.Clements@amd.com&gt;
Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Xiaojie Yuan &lt;xiaojie.yuan@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Split gpu_info_soc_bounding_box out from amdgpu_ucode.h</title>
<updated>2019-06-21T23:59:34Z</updated>
<author>
<name>Leo Li</name>
<email>sunpeng.li@amd.com</email>
</author>
<published>2019-04-03T21:20:49Z</published>
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<id>urn:sha1:57b3ec35d5df7ebec65c6472ea1cd9f6a764eb09</id>
<content type='text'>
DC needs to include the soc bounding box when initializing HW resources.

Including amdgpu_ucode.h directly will cause warnings, since amdgpu.h is
required to define amdgpu_device. The solution here is to split the
bounding box structs into a different header, then include it in both
amdgpu_ucode.h, and relevant DC HW resource files.

Signed-off-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Read soc_bounding_box from gpu_info (v2)</title>
<updated>2019-06-21T23:59:34Z</updated>
<author>
<name>Harry Wentland</name>
<email>harry.wentland@amd.com</email>
</author>
<published>2019-05-07T19:34:21Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=48321c3dde79f7f2db5000febddf70df3620c445'/>
<id>urn:sha1:48321c3dde79f7f2db5000febddf70df3620c445</id>
<content type='text'>
[WHY]
We don't want to expose sensitive ASIC information before ASIC release.

[HOW]
Encode the soc_bounding_box in the gpu_info FW (for Linux) and read it
at driver load.

v2: fix warning when CONFIG_DRM_AMD_DC_DCN2_0 is not set (Alex)

Signed-off-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add corresponding vcn ram ucode id</title>
<updated>2019-06-21T23:59:32Z</updated>
<author>
<name>Jack Xiao</name>
<email>Jack.Xiao@amd.com</email>
</author>
<published>2019-05-14T03:36:33Z</published>
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<id>urn:sha1:6e72d8e9fb70d3677b319949c41370781c148f4f</id>
<content type='text'>
Add VCN RAM ucode id in corresponding to psp ucode id.

Signed-off-by: Jack Xiao &lt;Jack.Xiao@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/ucode: add mes firmware file support</title>
<updated>2019-06-21T23:59:27Z</updated>
<author>
<name>Jack Xiao</name>
<email>Jack.Xiao@amd.com</email>
</author>
<published>2019-04-15T03:33:05Z</published>
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<id>urn:sha1:7f785e7843a4024aeb4c17c3ff53c395aca84d64</id>
<content type='text'>
The newly added firmware struct is for mes firmware file.

Signed-off-by: Jack Xiao &lt;Jack.Xiao@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/ucode: add the definitions of MES ucode and ucode data</title>
<updated>2019-06-21T23:59:27Z</updated>
<author>
<name>Jack Xiao</name>
<email>Jack.Xiao@amd.com</email>
</author>
<published>2019-04-12T06:23:44Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=186b0ca28293c599b425b84d90d3385e81df9702'/>
<id>urn:sha1:186b0ca28293c599b425b84d90d3385e81df9702</id>
<content type='text'>
MES requires two seperate firmwares: ucode and ucode data.

Signed-off-by: Jack Xiao &lt;Jack.Xiao@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/powerplay: implement smc firmware v2.1 for smu11</title>
<updated>2019-06-21T23:59:25Z</updated>
<author>
<name>Kevin Wang</name>
<email>kevin1.wang@amd.com</email>
</author>
<published>2019-06-21T15:49:22Z</published>
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<id>urn:sha1:b55c83a7438da50126e6a2c98dcf4476ce2fd0fd</id>
<content type='text'>
1.add smc_firmware_header_v2_1 hfirmware support, support more pptable in smc firmware.
2.optimization current pptable load framework.
3.rename read_pptable_from_vbios with setup_pptable.

Signed-off-by: Kevin Wang &lt;kevin1.wang@amd.com&gt;
Reviewed-by: Huang Rui &lt;ray.huang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
