<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c, branch v4.15</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v4.15</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v4.15'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2017-09-26T19:14:24Z</updated>
<entry>
<title>drm/amdgpu:fix uvd ring fini routine(v2)</title>
<updated>2017-09-26T19:14:24Z</updated>
<author>
<name>Monk Liu</name>
<email>Monk.Liu@amd.com</email>
</author>
<published>2017-09-15T08:43:01Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=4ff184d70e1dd85cc39f3b8ed0d98b728d6d9b6c'/>
<id>urn:sha1:4ff184d70e1dd85cc39f3b8ed0d98b728d6d9b6c</id>
<content type='text'>
fix missing finish uvd enc_ring.
v2:
since the adev pointer check in already in ring_fini
so drop the check outsider

Signed-off-by: Monk Liu &lt;Monk.Liu@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: move amdgpu_cs_sysvm_access_required into find_mapping</title>
<updated>2017-09-12T18:27:22Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2017-09-06T14:15:28Z</published>
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<id>urn:sha1:9cca0b8e5df0ac438c65eec5044bfa089d16fbbe</id>
<content type='text'>
When we need to find the mapping we need sysvm access anyway.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Acked-by: Leo Liu &lt;leo.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add MJPEG check for UVD physical mode msg buffer</title>
<updated>2017-08-17T20:47:44Z</updated>
<author>
<name>Leo Liu</name>
<email>leo.liu@amd.com</email>
</author>
<published>2017-08-15T14:57:34Z</published>
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<id>urn:sha1:d0b83d413f2254484d8e359c3eee2f0ca846e231</id>
<content type='text'>
Signed-off-by: Leo Liu &lt;leo.liu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add a parameter to amdgpu_bo_create()</title>
<updated>2017-08-15T18:45:58Z</updated>
<author>
<name>Yong Zhao</name>
<email>Yong.Zhao@amd.com</email>
</author>
<published>2017-07-20T22:49:09Z</published>
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<id>urn:sha1:2046d46db9166bddc84778f0b3477f6d1e9068ea</id>
<content type='text'>
The parameter init_value contains the value to which we initialized
VRAM bo when AMDGPU_GEM_CREATE_VRAM_CLEARED flag is set.

Signed-off-by: Yong Zhao &lt;Yong.Zhao@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: use a 64bit interval tree for VM management v2</title>
<updated>2017-04-04T17:40:32Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2017-03-30T12:03:59Z</published>
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<id>urn:sha1:a9f87f6452543505108d7d9b36d948534ea28b0b</id>
<content type='text'>
This only makes a difference for 32-bit systems. The idea is to have a
fixed virtual address space size with 4-level page tables and to
minimize differences between 32 and 64-bit systems.

v2: Update commit message.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Don't touch PG&amp;CG for SRIOV MM</title>
<updated>2017-03-30T03:55:08Z</updated>
<author>
<name>Xiangliang Yu</name>
<email>Xiangliang.Yu@amd.com</email>
</author>
<published>2017-03-07T06:45:25Z</published>
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<id>urn:sha1:d9af225942d5ac11b8c0aff4f9e25fd0524f5df6</id>
<content type='text'>
For SRIOV, MM don't need to care about PG &amp; CG, skip it.

Signed-off-by: Xiangliang Yu &lt;Xiangliang.Yu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Monk Liu &lt;Monk.Liu@amd.com&gt;
Reviewed-by: Christian KÃ¶nig &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add initial uvd 7.0 support for vega10</title>
<updated>2017-03-30T03:54:47Z</updated>
<author>
<name>Leo Liu</name>
<email>leo.liu@amd.com</email>
</author>
<published>2017-03-03T23:13:26Z</published>
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<id>urn:sha1:09bfb8912dc16383ce9f95600134d8eb120107f8</id>
<content type='text'>
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Leo Liu &lt;leo.liu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: when dpm disabled, also can enable uvd cg/pg.</title>
<updated>2017-02-08T22:20:03Z</updated>
<author>
<name>Rex Zhu</name>
<email>Rex.Zhu@amd.com</email>
</author>
<published>2017-01-20T04:06:05Z</published>
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<id>urn:sha1:e38ca2b3250f819b7dc12f82204db571232e7921</id>
<content type='text'>
Signed-off-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: remove the uncessary parameter for ib scheduler</title>
<updated>2017-01-27T17:20:37Z</updated>
<author>
<name>Junwei Zhang</name>
<email>Jerry.Zhang@amd.com</email>
</author>
<published>2017-01-23T08:30:38Z</published>
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<id>urn:sha1:50ddc75e32bba7cce994d530ec27aec697a372f8</id>
<content type='text'>
Signed-off-by: Junwei Zhang &lt;Jerry.Zhang@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: get maximum and used UVD handles (v4)</title>
<updated>2017-01-27T16:12:38Z</updated>
<author>
<name>Arindam Nath</name>
<email>arindam.nath@amd.com</email>
</author>
<published>2016-12-12T09:59:33Z</published>
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<id>urn:sha1:44879b6261530b14be339958a0f34805a8fa739a</id>
<content type='text'>
Change History
--------------

v4: Changes suggested by Emil, Christian
- return -ENODATA for asics with unlimited sessions

v3: changes suggested by Christian
- Add a check for UVD IP block using AMDGPU_HW_IP_UVD
  query type.
- Add a check for asic_type to be less than
  CHIP_POLARIS10 since starting Polaris, we support
  unlimited UVD instances.
- Add kerneldoc style comment for
  amdgpu_uvd_used_handles().

v2: as suggested by Christian
- Add a new query AMDGPU_INFO_NUM_HANDLES
- Create a helper function to return the number
  of currently used UVD handles.
- Modify the logic to count the number of used
  UVD handles since handles can be freed in
  non-linear fashion.

v1:
- User might want to query the maximum number of UVD
  instances supported by firmware. In addition to that,
  if there are multiple applications using UVD handles
  at the same time, he might also want to query the
  currently used number of handles.

  For this we add two variables max_handles and
  used_handles inside drm_amdgpu_info_hw_ip. So now
  an application (or libdrm) can use AMDGPU_INFO IOCTL
  with AMDGPU_INFO_HW_IP_INFO query type to get these
  values.

Signed-off-by: Arindam Nath &lt;arindam.nath@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
