<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c, branch v4.15</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v4.15</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v4.15'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2017-11-08T22:54:59Z</updated>
<entry>
<title>drm/amdgpu: potential uninitialized variable in amdgpu_vce_ring_parse_cs()</title>
<updated>2017-11-08T22:54:59Z</updated>
<author>
<name>Dan Carpenter</name>
<email>dan.carpenter@oracle.com</email>
</author>
<published>2017-09-30T08:13:28Z</published>
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<id>urn:sha1:40a9960b046290939b56ce8e51f365258f27f264</id>
<content type='text'>
We shifted some code around in commit 9cca0b8e5df0 ("drm/amdgpu: move
amdgpu_cs_sysvm_access_required into find_mapping") and now my static
checker complains that "r" might not be initialized at the end of the
function.  I've reviewed the code, and that seems possible, but it's
also possible I may have missed something.

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Dan Carpenter &lt;dan.carpenter@oracle.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu: move amdgpu_cs_sysvm_access_required into find_mapping</title>
<updated>2017-09-12T18:27:22Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2017-09-06T14:15:28Z</published>
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<id>urn:sha1:9cca0b8e5df0ac438c65eec5044bfa089d16fbbe</id>
<content type='text'>
When we need to find the mapping we need sysvm access anyway.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Acked-by: Leo Liu &lt;leo.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Skip uvd and vce ring test for SRIOV</title>
<updated>2017-08-15T18:45:47Z</updated>
<author>
<name>Frank Min</name>
<email>Frank.Min@amd.com</email>
</author>
<published>2017-06-12T03:02:09Z</published>
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<id>urn:sha1:a1b9022a3bfbdae234f2ec52b92e1566372ecd3f</id>
<content type='text'>
Since rptr would not be accessed on later secure asics in sriov, remove
the ring test.

Signed-off-by: Frank Min &lt;Frank.Min@amd.com&gt;
Signed-off-by: Xiangliang.Yu &lt;Xiangliang.Yu@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: use existing function amdgpu_bo_create_kernel</title>
<updated>2017-06-01T20:00:21Z</updated>
<author>
<name>Leo Liu</name>
<email>leo.liu@amd.com</email>
</author>
<published>2017-05-31T18:13:20Z</published>
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<id>urn:sha1:78b3c83983ce42067816a30825f9692eae952093</id>
<content type='text'>
To simplify vce bo create

Signed-off-by: Leo Liu &lt;leo.liu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/vce4: enable ring &amp; ib test for sriov</title>
<updated>2017-04-28T21:32:16Z</updated>
<author>
<name>Frank Min</name>
<email>Frank.Min@amd.com</email>
</author>
<published>2017-04-06T06:46:50Z</published>
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<id>urn:sha1:0381631299e54128be5180d0a169b06cd3ce1ba6</id>
<content type='text'>
Now VCE block can work for SRIOV, enable ring &amp; ib test.

Signed-off-by: Frank Min &lt;Frank.Min@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/vce4: workaround VCE ring test slow issue</title>
<updated>2017-04-28T21:32:15Z</updated>
<author>
<name>Xiangliang Yu</name>
<email>Xiangliang.Yu@amd.com</email>
</author>
<published>2017-04-06T06:43:48Z</published>
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<id>urn:sha1:a2f537e03b678887fdd8d0810b03ecad01ba5d36</id>
<content type='text'>
Add VCE ring test slow workaround for SRIOV.

Signed-off-by: Frank Min &lt;Frank.Min@amd.com&gt;
Signed-off-by: Xiangliang Yu &lt;Xiangliang.Yu@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: use a 64bit interval tree for VM management v2</title>
<updated>2017-04-04T17:40:32Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2017-03-30T12:03:59Z</published>
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<id>urn:sha1:a9f87f6452543505108d7d9b36d948534ea28b0b</id>
<content type='text'>
This only makes a difference for 32-bit systems. The idea is to have a
fixed virtual address space size with 4-level page tables and to
minimize differences between 32 and 64-bit systems.

v2: Update commit message.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/vce4: Ignore vce ring/ib test temporarily</title>
<updated>2017-03-30T03:55:11Z</updated>
<author>
<name>Xiangliang Yu</name>
<email>Xiangliang.Yu@amd.com</email>
</author>
<published>2017-03-08T06:35:16Z</published>
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<id>urn:sha1:e76347b0c2c5c23150d331aad8d8a2dffafeee6a</id>
<content type='text'>
In order to not break SRIOV gfx development, will revert
this patch after vce proved working.

Signed-off-by: Xiangliang Yu &lt;Xiangliang.Yu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Monk Liu &lt;Monk.Liu@amd.com&gt;
Reviewed-by: Christian KÃ¶nig &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Don't touch PG&amp;CG for SRIOV MM</title>
<updated>2017-03-30T03:55:08Z</updated>
<author>
<name>Xiangliang Yu</name>
<email>Xiangliang.Yu@amd.com</email>
</author>
<published>2017-03-07T06:45:25Z</published>
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<id>urn:sha1:d9af225942d5ac11b8c0aff4f9e25fd0524f5df6</id>
<content type='text'>
For SRIOV, MM don't need to care about PG &amp; CG, skip it.

Signed-off-by: Xiangliang Yu &lt;Xiangliang.Yu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Monk Liu &lt;Monk.Liu@amd.com&gt;
Reviewed-by: Christian KÃ¶nig &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add initial vce 4.0 support for vega10</title>
<updated>2017-03-30T03:54:47Z</updated>
<author>
<name>Leo Liu</name>
<email>leo.liu@amd.com</email>
</author>
<published>2017-03-03T23:27:49Z</published>
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<id>urn:sha1:c1dc356a116c992433c5c68e7c493b0fa3e6f9b1</id>
<content type='text'>
Signed-off-by: Leo Liu &lt;leo.liu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
