linux/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c, branch v5.3Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
https://git.shady.money/linux/atom?h=v5.32019-06-25T13:42:25ZMerge branch 'drm-next' into drm-next-5.32019-06-25T13:42:25ZAlex Deucheralexander.deucher@amd.com2019-06-25T13:42:25Zurn:sha1:d7929c1e13e3788e7cb741d75b5baec5e53eff21
Backmerge drm-next and fix up conflicts due to drmP.h removal.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/VCN: enable indirect DPG SRAM mode2019-06-21T23:59:33ZLeo Liuleo.liu@amd.com2019-05-27T14:49:19Zurn:sha1:450af30ce23a6fca66686855255a69d9179f42c4
This is default mode for VCN2.x now
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/VCN: add buffer for indirect SRAM usage2019-06-21T23:59:33ZLeo Liuleo.liu@amd.com2019-05-24T18:07:41Zurn:sha1:a77b9fdf9aca3d9d8955487e95cd1e884b45fe1a
This will be used later for indirect SRAM mode
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: enable vcn dpm scheme for navi2019-06-21T23:59:27ZJack XiaoJack.Xiao@amd.com2019-04-18T10:11:55Zurn:sha1:6e4cb4e8b31faf12575ac01dac47d2f87f9ac245
On navi1x, vcn dpm scheme was merged into powergating scheme.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/powerplay: set dpm_enabled flag but don't enable vcn dpm2019-06-21T23:59:27ZHuang Ruiray.huang@amd.com2019-05-30T04:18:01Zurn:sha1:948f540cd0120ef9d622af42c1b95f28cf992da0
This patch sets dpm_enabled flag but don't enable vcn dpm, because vcn dpm
doesn't work so far and we needs to enable the sysfs interfaces.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add JPEG2.0 decode ring ib test2019-06-21T23:58:22ZLeo Liuleo.liu@amd.com2018-10-15T20:17:27Zurn:sha1:54bb93c2251ce8fcfd44db491e85f01c17025fb5
Add internal register offset for registers involving in ib tests
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add JPEG2.0 decode ring test2019-06-21T23:58:22ZLeo Liuleo.liu@amd.com2018-12-03T16:42:28Zurn:sha1:9085914a5af4b3078a0289c4d67ee7cbc45dac99
Use register from JPEG tile, the UVD tile reg won't work for JPEG
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add VCN2.0 decode ib test2019-06-21T23:58:22ZLeo Liuleo.liu@amd.com2018-10-15T19:41:36Zurn:sha1:60a2309ec465aab22910ddce8e45aaa624f87f5d
Add internal register offset for registers involving in ib tests
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add VCN2.0 decode ring test2019-06-21T23:58:22ZLeo Liuleo.liu@amd.com2018-10-17T18:33:48Zurn:sha1:45a1a48b5c310700d338105df5883e8f8ab1f994
Add internal register offset for registers involving in ring tests
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add Navi10 VCN firmware support2019-06-21T23:58:22ZLeo Liuleo.liu@amd.com2018-10-15T19:07:08Zurn:sha1:a8790e2475ea48a06d8834db7717f7f715a77366
Add Navi10 to VCN family
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>