linux/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c, branch v4.20

drm/amdgpu: correctly sign extend 48bit addresses v3

2018-09-11T03:41:24Z

Correct sign extend the GMC addresses to 48bit. v2: sign extending turned out easier than thought. v3: clean up the defines and move them into amdgpu_gmc.h as well Signed-off-by: Christian König Reviewed-by: Junwei Zhang Signed-off-by: Alex Deucher

drm/amdgpu: use kiq to do invalidate tlb

2018-08-27T16:11:08Z

To avoid the tlb flush not interrupted by world switch, use kiq and one command to do tlb invalidate. v2: Refine the invalidate lock position. Signed-off-by: Emily Deng Reviewed-and-Tested-by: Rex Zhu Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: give warning before sleep in kiq_r/wreg

2018-03-07T21:10:13Z

to catch error that may schedule in atomic context early on Signed-off-by: Monk Liu Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: try again kiq access if not in IRQ(v4)

2018-03-01T17:04:17Z

sometimes GPU is switched to other VFs and won't swich back soon, so the kiq reg access will not signal within a short period, instead of busy waiting a long time(MAX_KEQ_REG_WAIT) and returning TMO we can istead sleep 5ms and try again later (non irq context) And since the waiting in kiq_r/weg is busy wait, so MAX_KIQ_REG_WAIT shouldn't set to a long time, set it to 10ms is more appropriate. if gpu already in reset state, don't retry the KIQ reg access otherwise it would always hang because KIQ was already die usually. v2: replace schedule() with msleep() for the wait v3: use while loop for the wait repeating use macros for the sleep period more description for it v4: drop unused variable Signed-off-by: Monk Liu Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: move static CSA address to top of address space v2

2018-02-19T19:18:48Z

Move the CSA area to the top of the VA space to avoid clashing with HMM/ATC in the lower range on GFX9. v2: wrong sign noticed by Roger, rebase on CSA_VADDR cleanup, handle VA hole on GFX9 as well. Signed-off-by: Christian König Acked-by: Alex Deucher Acked-by: Monk Liu Signed-off-by: Alex Deucher

drm/amdgpu:free CSA in unified place

2017-12-06T17:47:51Z

instead of doing it in each GFX ip's sw_fini Signed-off-by: Monk Liu Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu/virt: remove redundant variable pf2vf_ver

2017-12-06T17:47:23Z

Variable pf2vf_ver is assigned but never read, it is redundant and hence can be removed. Cleans up clang warning: drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:310:3: warning: Value stored to 'pf2vf_ver' is never read Reivewed-by: Horace Chen Signed-off-by: Colin Ian King Signed-off-by: Alex Deucher

drm/amdgpu:read VRAMLOST from gim

2017-12-04T21:41:45Z

Signed-off-by: Monk Liu Acked-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu:cleanup in_sriov_reset and lock_reset

2017-12-04T21:41:31Z

since now gpu reset is unified with gpu_recover for both bare-metal and SR-IOV: 1)rename in_sriov_reset to in_gpu_reset 2)move lock_reset from adev->virt to adev Signed-off-by: Monk Liu Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu/virt: add wait_reset virt ops

2017-12-04T21:33:13Z

Driver can use this interface to check if there's a function level reset done in hypervisor. It's helpful when IRQ handler for reset is not ready, or special handling is required. Acked-by: Alex Deucher Reviewed-by: Monk Liu Signed-off-by: pding Signed-off-by: Alex Deucher