<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c, branch v5.14</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.14</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.14'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2021-05-20T02:33:58Z</updated>
<entry>
<title>drm/amdgpu: Fill adev-&gt;unique_id with data from PF2VF msg</title>
<updated>2021-05-20T02:33:58Z</updated>
<author>
<name>Jiawei Gu</name>
<email>Jiawei.Gu@amd.com</email>
</author>
<published>2021-05-13T06:17:58Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=5228cd65742abd2221d7bdb622544ac47e41d87c'/>
<id>urn:sha1:5228cd65742abd2221d7bdb622544ac47e41d87c</id>
<content type='text'>
Initialize unique_id from PF2VF under virtualization.

V2: skip smu_get_unique_id() under virtualization

Signed-off-by: Jiawei Gu &lt;Jiawei.Gu@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Complete multimedia bandwidth interface</title>
<updated>2021-05-20T02:29:58Z</updated>
<author>
<name>Bokun Zhang</name>
<email>bokun.zhang@amd.com</email>
</author>
<published>2021-05-13T05:17:54Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=ed9d205363c3ec786126e46568e9e9aadaf0cb93'/>
<id>urn:sha1:ed9d205363c3ec786126e46568e9e9aadaf0cb93</id>
<content type='text'>
- Update SRIOV PF2VF header with latest revision

- Extend existing function in amdgpu_virt.c to read MM bandwidth config
  from PF2VF message

- Add SRIOV Sienna Cichlid codec array and update the bandwidth with
  PF2VF message

v2: squash in removal of unused variable (Alex)

Signed-off-by: Bokun Zhang &lt;bokun.zhang@amd.com&gt;
Reviewed-by: Monk liu &lt;monk.liu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add Aldebaran virtualization support</title>
<updated>2021-05-10T22:06:43Z</updated>
<author>
<name>Zhigang Luo</name>
<email>zhigang.luo@amd.com</email>
</author>
<published>2021-04-29T19:37:31Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=e7de0d844ea803d752e0b41e6b7dcc35d671c186'/>
<id>urn:sha1:e7de0d844ea803d752e0b41e6b7dcc35d671c186</id>
<content type='text'>
1. add Aldebaran in virtualization detection list.
2. disable Aldebaran virtual display support as there is no GFX
   engine in Aldebaran.
3. skip TMR loading if Aldebaran is in virtualizatin mode as it
   shares the one host loaded.

Signed-off-by: Zhigang Luo &lt;zhigang.luo@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: indirect register access for nv12 sriov</title>
<updated>2021-04-09T20:50:13Z</updated>
<author>
<name>Peng Ju Zhou</name>
<email>PengJu.Zhou@amd.com</email>
</author>
<published>2021-03-30T10:27:15Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=5d23851029b78fb6d6d56a40300676d49a0ce609'/>
<id>urn:sha1:5d23851029b78fb6d6d56a40300676d49a0ce609</id>
<content type='text'>
using the control bits got from host to control registers access.

Signed-off-by: Peng Ju Zhou &lt;PengJu.Zhou@amd.com&gt;
Reviewed-by: Emily.Deng &lt;Emily.Deng@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: indirect register access for nv12 sriov</title>
<updated>2021-04-09T20:50:09Z</updated>
<author>
<name>Peng Ju Zhou</name>
<email>PengJu.Zhou@amd.com</email>
</author>
<published>2021-03-29T07:47:20Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=77eabc6f5975dafeb76f7c7c2451282b91e9f5b6'/>
<id>urn:sha1:77eabc6f5975dafeb76f7c7c2451282b91e9f5b6</id>
<content type='text'>
get pf2vf msg info at it's earliest time so that
guest driver can use these info to decide whether
register indirect access enabled.

Signed-off-by: Peng Ju Zhou &lt;PengJu.Zhou@amd.com&gt;
Reviewed-by: Emily.Deng &lt;Emily.Deng@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: detect sriov capability for aldebaran</title>
<updated>2021-03-24T02:52:27Z</updated>
<author>
<name>Hawking Zhang</name>
<email>Hawking.Zhang@amd.com</email>
</author>
<published>2020-05-25T08:20:35Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=1b15bac7bfdae2d77c631144066e32b3df3d778c'/>
<id>urn:sha1:1b15bac7bfdae2d77c631144066e32b3df3d778c</id>
<content type='text'>
SRIOV pf/vf function identifier regsiter in aldebaran
is the same as the one in arcturus

Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Kevin Wang &lt;kevin1.wang@amd.com&gt;
Reviewed-by: Le Ma &lt;Le.Ma@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: add error handling to amdgpu_virt_read_pf2vf_data</title>
<updated>2021-01-25T22:46:48Z</updated>
<author>
<name>Jingwen Chen</name>
<email>Jingwen.Chen2@amd.com</email>
</author>
<published>2021-01-19T08:54:50Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=64dcf2f01d59cf9fad19b1a387bd39736a8f4d69'/>
<id>urn:sha1:64dcf2f01d59cf9fad19b1a387bd39736a8f4d69</id>
<content type='text'>
[Why]
when vram lost happened in guest, try to write vram can lead to
kernel stuck.

[How]
When the readback data is invalid, don't do write work, directly
reschedule a new work.

Signed-off-by: Jingwen Chen &lt;Jingwen.Chen2@amd.com&gt;
Reviewed-by: Monk Liu&lt;monk.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: remove redundant flush_delayed_work</title>
<updated>2021-01-20T21:38:17Z</updated>
<author>
<name>Jingwen Chen</name>
<email>Jingwen.Chen2@amd.com</email>
</author>
<published>2021-01-18T02:30:36Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=b43ae488ac3191feb119ffdda22d28f72a99c1e3'/>
<id>urn:sha1:b43ae488ac3191feb119ffdda22d28f72a99c1e3</id>
<content type='text'>
When using cancel_delayed_work_sync, there's no need
to flush_delayed_work first. This sequence can lead to
a redundant loop of work executing.

Signed-off-by: Jingwen Chen &lt;Jingwen.Chen2@amd.com&gt;
Reviewed-by: Monk Liu &lt;monk.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/sriov Stop data exchange for wholegpu reset</title>
<updated>2021-01-14T04:47:39Z</updated>
<author>
<name>Jack Zhang</name>
<email>Jack.Zhang1@amd.com</email>
</author>
<published>2021-01-07T10:38:29Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=3c2a01cb0fc567c18b802f25d619e31c196294ce'/>
<id>urn:sha1:3c2a01cb0fc567c18b802f25d619e31c196294ce</id>
<content type='text'>
[Why]
When host trigger a whole gpu reset, guest will keep
waiting till host finish reset. But there's a work
queue in guest exchanging data between vf&amp;pf which need
to access frame buffer. During whole gpu reset, frame
buffer is not accessable, and this causes the call trace.

[How]
After vf get reset notification from pf, stop data exchange.

Signed-off-by: Jingwen Chen &lt;Jingwen.Chen2@amd.com&gt;
Signed-off-by: Jack Zhang &lt;Jack.Zhang1@amd.com&gt;
Reviewed-by: Monk Liu &lt;monk.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'amd-drm-next-5.11-2020-12-09' of git://people.freedesktop.org/~agd5f/linux into drm-next</title>
<updated>2020-12-10T06:55:53Z</updated>
<author>
<name>Dave Airlie</name>
<email>airlied@redhat.com</email>
</author>
<published>2020-12-10T06:55:41Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=b10733527bfd864605c33ab2e9a886eec317ec39'/>
<id>urn:sha1:b10733527bfd864605c33ab2e9a886eec317ec39</id>
<content type='text'>
amd-drm-next-5.11-2020-12-09:

amdgpu:
- SR-IOV fixes
- Navy Flounder updates
- Sienna Cichlid updates
- Dimgrey Cavefish updates
- Vangogh updates
- Misc SMU fixes
- Misc display fixes
- Last big hunk of W=1 warning fixes
- Cursor validation fixes
- CI BACO updates

From: Alex Deucher &lt;alexdeucher@gmail.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20201210045344.21566-1-alexander.deucher@amd.com
Signed-off-by: Dave Airlie &lt;airlied@redhat.com&gt;
</content>
</entry>
</feed>
