linux/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c, branch v5.8

drm/amdgpu: add amdgpu_virt_get_vf_mode helper function

2020-05-18T15:23:52Z

the swsmu or powerplay(hwmgr) need to handle task according to different VF mode, this function to help query vf mode. vf mode: 1. SRIOV_VF_MODE_BARE_METAL: the driver work on host OS (PF) 2. SRIOV_VF_MODE_ONE_VF : the driver work on guest OS with one VF 3. SRIOV_VF_MODE_MULTI_VF : the driver work on guest OS with multi VF Signed-off-by: Kevin Wang Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher

drm/amdgpu: protect ring overrun

2020-04-24T15:42:11Z

Wait for the oldest sequence on the ring to be signaled in order to make sure there will be no command overrun. v2: fix coding stype and remove abs operation v3: remove the initialization of variable r Signed-off-by: Yintian Tao Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: resume kiq access debugfs

2020-04-13T16:01:56Z

If there is no GPU hang, user still can access debugfs through kiq. Signed-off-by: Yintian Tao Reviewed-by: Monk Liu Signed-off-by: Alex Deucher

drm/amdgpu: restrict debugfs register access under SR-IOV

2020-04-13T16:01:04Z

Under bare metal, there is no more else to take care of the GPU register access through MMIO. Under Virtualization, to access GPU register is implemented through KIQ during run-time due to world-switch. Therefore, under SR-IOV user can only access debugfs to r/w GPU registers when meets all three conditions below. - amdgpu_gpu_recovery=0 - TDR happened - in_gpu_reset=0 v2: merge amdgpu_virt_can_access_debugfs() into amdgpu_virt_enable_access_debugfs() v3: drop ret variable in amdgpu_virt_enable_access_debugfs() and directly return result Signed-off-by: Yintian Tao Acked-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu: introduce new request and its function

2020-04-01T18:44:43Z

1) modify xgpu_nv_send_access_requests to support new idh request 2) introduce new function: req_gpu_init_data() which is used to notify host to prepare vbios/ip-discovery/pfvf exchange Signed-off-by: Monk Liu Reviewed-by: Emily Deng Signed-off-by: Alex Deucher

drm/amdgpu: Virtual display need to support multiple ctrcs

2020-04-01T18:44:42Z

The crtc num is determined by virtual_display parameter. Signed-off-by: Emily Deng Reviewed-by: Monk Liu Signed-off-by: Alex Deucher

drm/amdgpu: cleanup all virtualization detection routine

2020-04-01T18:44:42Z

we need to move virt detection much earlier because: 1) HW team confirms us that RCC_IOV_FUNC_IDENTIFIER will always be at DE5 (dw) mmio offset from vega10, this way there is no need to implement detect_hw_virt() routine in each nbio/chip file. for VI SRIOV chip (tonga & fiji), the BIF_IOV_FUNC_IDENTIFIER is at 0x1503 2) we need to acknowledged we are SRIOV VF before we do IP discovery because the IP discovery content will be updated by host everytime after it recieved a new coming "REQ_GPU_INIT_DATA" request from guest (there will be patches for this new handshake soon). Signed-off-by: Monk Liu Reviewed-by: Emily Deng Signed-off-by: Alex Deucher

drm/amdgpu: provide a generic function interface for reading/writing register by KIQ

2020-01-22T21:34:14Z

Move amdgpu_virt_kiq_rreg/amdgpu_virt_kiq_wreg function to amdgpu_gfx.c, and rename them to amdgpu_kiq_rreg/amdgpu_kiq_wreg.Make it generic and flexible. Signed-off-by: chen gong Reviewed-by: Alex Deucher Reviewed-by: Huang Rui Acked-by: Christian König Signed-off-by: Alex Deucher

drm/amd/powerplay: enable pp one vf mode for vega10

2019-12-11T20:22:07Z

Originally, due to the restriction from PSP and SMU, VF has to send message to hypervisor driver to handle powerplay change which is complicated and redundant. Currently, SMU and PSP can support VF to directly handle powerplay change by itself. Therefore, the old code about the handshake between VF and PF to handle powerplay will be removed and VF will use new the registers below to handshake with SMU. mmMP1_SMN_C2PMSG_101: register to handle SMU message mmMP1_SMN_C2PMSG_102: register to handle SMU parameter mmMP1_SMN_C2PMSG_103: register to handle SMU response v2: remove module parameter pp_one_vf v3: fix the parens v4: forbid vf to change smu feature v5: use hwmon_attributes_visible to skip sepicified hwmon atrribute v6: change skip condition at vega10_copy_table_to_smc Signed-off-by: Yintian Tao Acked-by: Evan Quan Reviewed-by: Kenneth Feng Signed-off-by: Alex Deucher

drm/amdgpu: cleanup vega10 SRIOV code path

2019-08-02T15:17:21Z

we can simplify all those unnecessary function under SRIOV for vega10 since: 1) PSP L1 policy is by force enabled in SRIOV 2) original logic always set all flags which make itself a dummy step besides, 1) the ih_doorbell_range set should also be skipped for VEGA10 SRIOV. 2) the gfx_common registers should also be skipped for VEGA10 SRIOV. Signed-off-by: Monk Liu Reviewed-by: Emily Deng Signed-off-by: Alex Deucher