<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c, branch v6.0</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v6.0</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v6.0'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2022-06-30T19:28:24Z</updated>
<entry>
<title>drm/amdgpu: enable mes to access registers v2</title>
<updated>2022-06-30T19:28:24Z</updated>
<author>
<name>Jack Xiao</name>
<email>Jack.Xiao@amd.com</email>
</author>
<published>2022-06-16T13:34:24Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=cf6067290034b9ebbe4c39733b1a4acc94876c26'/>
<id>urn:sha1:cf6067290034b9ebbe4c39733b1a4acc94876c26</id>
<content type='text'>
Enable mes to access registers.

v2: squash mes sched ring enablement flag

Signed-off-by: Jack Xiao &lt;Jack.Xiao@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: do not use passthrough mode in Xen dom0</title>
<updated>2022-04-28T21:46:01Z</updated>
<author>
<name>Marek Marczykowski-Górecki</name>
<email>marmarek@invisiblethingslab.com</email>
</author>
<published>2022-04-26T23:57:15Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=78b12008f20490655e360bcb2e043aa5b9580174'/>
<id>urn:sha1:78b12008f20490655e360bcb2e043aa5b9580174</id>
<content type='text'>
While technically Xen dom0 is a virtual machine too, it does have
access to most of the hardware so it doesn't need to be considered a
"passthrough". Commit b818a5d37454 ("drm/amdgpu/gmc: use PCI BARs for
APUs in passthrough") changed how FB is accessed based on passthrough
mode. This breaks amdgpu in Xen dom0 with message like this:

    [drm:dc_dmub_srv_wait_idle [amdgpu]] *ERROR* Error waiting for DMUB idle: status=3

While the reason for this failure is unclear, the passthrough mode is
not really necessary in Xen dom0 anyway. So, to unbreak booting affected
kernels, disable passthrough mode in this case.

Link: https://gitlab.freedesktop.org/drm/amd/-/issues/1985
Fixes: b818a5d37454 ("drm/amdgpu/gmc: use PCI BARs for APUs in passthrough")
Signed-off-by: Marek Marczykowski-Górecki &lt;marmarek@invisiblethingslab.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: Remove static from variable in RLCG Reg RW</title>
<updated>2022-04-14T19:29:20Z</updated>
<author>
<name>Gavin Wan</name>
<email>Gavin.Wan@amd.com</email>
</author>
<published>2022-04-13T15:09:22Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=d68cf992ded575928cf4ddf7c64faff0d8dcce14'/>
<id>urn:sha1:d68cf992ded575928cf4ddf7c64faff0d8dcce14</id>
<content type='text'>
[why]
These static variables save the RLC Scratch registers address.
When we install multiple GPUs (for example: XGMI setting) and
multiple GPUs call the function at same time. The RLC Scratch
registers address are changed each other. Then it caused
reading/writing from/to wrong GPU.

[how]
Removed the static from the variables. The variables are
on the stack.

Fixes: 5d447e29670148 ("drm/amdgpu: add helper for rlcg indirect reg access")
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Gavin Wan &lt;Gavin.Wan@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: Not request init data for MS_HYPERV with vega10</title>
<updated>2022-04-13T13:14:22Z</updated>
<author>
<name>Yongqiang Sun</name>
<email>yongqiang.sun@amd.com</email>
</author>
<published>2022-04-08T14:53:14Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=eb85fc238970afe4a309bb307bdeecc2938ba7b2'/>
<id>urn:sha1:eb85fc238970afe4a309bb307bdeecc2938ba7b2</id>
<content type='text'>
MS_HYPERV with vega10 doesn't have the interface to process
request init data msg.

Check hypervisor type to not send the request for MS_HYPERV.

Signed-off-by: Yongqiang Sun &lt;yongqiang.sun@amd.com&gt;
Reviewed-by: Alice Wong &lt;shiwei.wong@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Fix spelling mistake "regiser" -&gt; "register"</title>
<updated>2022-03-25T16:40:26Z</updated>
<author>
<name>Colin Ian King</name>
<email>colin.i.king@gmail.com</email>
</author>
<published>2022-03-15T20:19:59Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=2f78f0d3e3a89e76a7fe184fdef19efd85063f61'/>
<id>urn:sha1:2f78f0d3e3a89e76a7fe184fdef19efd85063f61</id>
<content type='text'>
There is a spelling mistake in a dev_error error message. Fix it.

Signed-off-by: Colin Ian King &lt;colin.i.king@gmail.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'drm-misc-next-2022-02-23' of git://anongit.freedesktop.org/drm/drm-misc into drm-next</title>
<updated>2022-02-24T19:50:18Z</updated>
<author>
<name>Dave Airlie</name>
<email>airlied@redhat.com</email>
</author>
<published>2022-02-24T19:30:17Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=54f43c17d681f6d9523fcfaeefc9df77993802e1'/>
<id>urn:sha1:54f43c17d681f6d9523fcfaeefc9df77993802e1</id>
<content type='text'>
drm-misc-next for v5.18:

UAPI Changes:

Cross-subsystem Changes:
- Split out panel-lvds and lvds dt bindings .
- Put yes/no on/off disabled/enabled strings in linux/string_helpers.h
  and use it in drivers and tomoyo.
- Clarify dma_fence_chain and dma_fence_array should never include eachother.
- Flatten chains in syncobj's.
- Don't double add in fbdev/defio when page is already enlisted.
- Don't sort deferred-I/O pages by default in fbdev.

Core Changes:
- Fix missing pm_runtime_put_sync in bridge.
- Set modifier support to only linear fb modifier if drivers don't
  advertise support.
- As a result, we remove allow_fb_modifiers.
- Add missing clear for EDID Deep Color Modes in drm_reset_display_info.
- Assorted documentation updates.
- Warn once in drm_clflush if there is no arch support.
- Add missing select for dp helper in drm_panel_edp.
- Assorted small fixes.
- Improve fb-helper's clipping handling.
- Don't dump shmem mmaps in a core dump.
- Add accounting to ttm resource manager, and use it in amdgpu.
- Allow querying the detected eDP panel through debugfs.
- Add helpers for xrgb8888 to 8 and 1 bits gray.
- Improve drm's buddy allocator.
- Add selftests for the buddy allocator.

Driver Changes:
- Add support for nomodeset to a lot of drm drivers.
- Use drm_module_*_driver in a lot of drm drivers.
- Assorted small fixes to bridge/lt9611, v3d, vc4, vmwgfx, mxsfb, nouveau,
  bridge/dw-hdmi, panfrost, lima, ingenic, sprd, bridge/anx7625, ti-sn65dsi86.
- Add bridge/it6505.
- Create DP and DVI-I connectors in ast.
- Assorted nouveau backlight fixes.
- Rework amdgpu reset handling.
- Add dt bindings for ingenic,jz4780-dw-hdmi.
- Support reading edid through aux channel in ingenic.
- Add a drm driver for Solomon SSD130x OLED displays.
- Add simple support for sharp LQ140M1JW46.
- Add more panels to nt35560.

Signed-off-by: Dave Airlie &lt;airlied@redhat.com&gt;

From: Maarten Lankhorst &lt;maarten.lankhorst@linux.intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/686ec871-e77f-c230-22e5-9e3bb80f064a@linux.intel.com
</content>
</entry>
<entry>
<title>drm/amdgpu: Fix wait for RLCG command completion</title>
<updated>2022-02-16T22:30:02Z</updated>
<author>
<name>Victor Skvortsov</name>
<email>victor.skvortsov@amd.com</email>
</author>
<published>2022-02-03T21:13:40Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=aa79d3808e8cf1f5fd0f1c20c2e6a6865b5b940c'/>
<id>urn:sha1:aa79d3808e8cf1f5fd0f1c20c2e6a6865b5b940c</id>
<content type='text'>
if (!(tmp &amp; flag)) condition will always evaluate to true
when the flag is 0x0 (AMDGPU_RLCG_GC_WRITE). Instead check
that address bits are cleared to determine whether
the command is complete.

Signed-off-by: Victor Skvortsov &lt;victor.skvortsov@amd.com&gt;
Tested-by: Bokun Zhang &lt;bokun.zhang@amd.com&gt;
Reviewed by: Shaoyun.liu &lt;Shaoyun.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: no rlcg legacy read in SRIOV case</title>
<updated>2022-02-14T20:08:40Z</updated>
<author>
<name>Guchun Chen</name>
<email>guchun.chen@amd.com</email>
</author>
<published>2022-02-10T06:34:51Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=22b1df28c009aaf78e77b20a9cc8d8bf98e698c8'/>
<id>urn:sha1:22b1df28c009aaf78e77b20a9cc8d8bf98e698c8</id>
<content type='text'>
rlcg legacy read is not available in SRIOV configration.
Otherwise, gmc_v9_0_flush_gpu_tlb will always complain
timeout and finally breaks driver load.

v2: bypass read in amdgpu_virt_get_rlcg_reg_access_flag (from Victor)

Fixes: 97d1a3b967a3cb ("drm/amdgpu: switch to get_rlcg_reg_access_flag for gfx9")
Signed-off-by: Guchun Chen &lt;guchun.chen@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Victor Skvortsov &lt;Victor.Skvortsov@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: remove VRAM accounting v2</title>
<updated>2022-02-14T14:05:39Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2021-07-12T13:37:01Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=7db47b838896ec2bb57e3d0b329804b84f32626c'/>
<id>urn:sha1:7db47b838896ec2bb57e3d0b329804b84f32626c</id>
<content type='text'>
This is provided by TTM now.

Also switch man-&gt;size to bytes instead of pages and fix the double
printing of size and usage in debugfs.

v2: fix size checking as well

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Tested-by: Bas Nieuwenhuizen &lt;bas@basnieuwenhuizen.nl&gt;
Reviewed-by: Matthew Auld &lt;matthew.auld@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20220214093439.2989-8-christian.koenig@amd.com
</content>
</entry>
<entry>
<title>drm/amdgpu: drop flood print in rlcg reg access function</title>
<updated>2022-02-02T23:26:31Z</updated>
<author>
<name>Guchun Chen</name>
<email>guchun.chen@amd.com</email>
</author>
<published>2022-01-28T15:14:07Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=274b924c3ed18f7d46d237810dd59d3bc89cb4b4'/>
<id>urn:sha1:274b924c3ed18f7d46d237810dd59d3bc89cb4b4</id>
<content type='text'>
A lot of below message are outputed in SRIOV case.
amdgpu: indirect registers access through rlcg is not supported

Also drop redundant ret set, as it's initialized to be false already.

Fixes: 29dbcac82f96d0 ("drm/amdgpu: add helper to query rlcg reg access flag")
Signed-off-by: Guchun Chen &lt;guchun.chen@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
