<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c, branch v6.8</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v6.8</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v6.8'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2023-12-13T20:09:53Z</updated>
<entry>
<title>drm/amdgpu: Use the right method to get IP version</title>
<updated>2023-12-13T20:09:53Z</updated>
<author>
<name>Lijo Lazar</name>
<email>lijo.lazar@amd.com</email>
</author>
<published>2023-12-01T11:43:46Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=ed342a2e78c4e4a8d82c2d19c95e8a3eb092c0d0'/>
<id>urn:sha1:ed342a2e78c4e4a8d82c2d19c95e8a3eb092c0d0</id>
<content type='text'>
Replace direct usage of adev-&gt;ip_versions with amdgpu_ip_version.

Signed-off-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Use correct KIQ MEC engine for gfx9.4.3 (v5)</title>
<updated>2023-11-09T22:03:07Z</updated>
<author>
<name>Victor Lu</name>
<email>victorchengchi.lu@amd.com</email>
</author>
<published>2023-10-03T20:15:52Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=85150626ea0423fd0adb5ac9b5ab4bbaff9aa30b'/>
<id>urn:sha1:85150626ea0423fd0adb5ac9b5ab4bbaff9aa30b</id>
<content type='text'>
amdgpu_kiq_wreg/rreg is hardcoded to use MEC engine 0.

Add an xcc_id parameter to amdgpu_kiq_wreg/rreg, define W/RREG32_XCC
and amdgpu_device_xcc_wreg/rreg to use the new xcc_id parameter.

Using amdgpu_sriov_runtime to determine whether to access via kiq or
RLC is sufficient for now.

v5: add condition in amdgpu_device_xcc_w/rreg, remove trace func call

v4: avoid using amdgpu_sriov_w/rreg

v3: use W/RREG32_XCC to handle non-kiq case

v2: define amdgpu_device_xcc_wreg/rreg instead of changing parameters
    of amdgpu_device_wreg/rreg

Signed-off-by: Victor Lu &lt;victorchengchi.lu@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add xcc param to SRIOV kiq write and WREG32_SOC15_IP_NO_KIQ (v4)</title>
<updated>2023-11-09T22:01:10Z</updated>
<author>
<name>Victor Lu</name>
<email>victorchengchi.lu@amd.com</email>
</author>
<published>2023-08-08T17:57:16Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=bc3c566071c8504f5d7c73a4171ead394f097639'/>
<id>urn:sha1:bc3c566071c8504f5d7c73a4171ead394f097639</id>
<content type='text'>
WREG32/RREG32_SOC15_IP_NO_KIQ and amdgpu_virt_kiq_reg_write_reg_wait
are not using the correct rlcg interface or mec engine, respectively.

Add xcc instance parameter to them.

v4: Use GET_INST and squash commit with:
"drm/amdgpu: Add xcc_inst param to amdgpu_virt_kiq_reg_write_reg_wait"

v3: xcc not needed for MMMHUB

v2: rebase

Signed-off-by: Victor Lu &lt;victorchengchi.lu@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd: Disable XNACK on SRIOV environment</title>
<updated>2023-11-07T16:15:37Z</updated>
<author>
<name>Surbhi Kakarya</name>
<email>surbhi.kakarya@amd.com</email>
</author>
<published>2023-09-25T16:12:10Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=9256e8d47a2fa0bcb5d32e7fee8c674c476a480f'/>
<id>urn:sha1:9256e8d47a2fa0bcb5d32e7fee8c674c476a480f</id>
<content type='text'>
The purpose of this patch is to disable XNACK or set XNACK OFF mode
on SRIOV platform which doesn't support it.

This will prevent user-space application to fail or result into
unexpected behaviour whenever the application need to run test-case
in XNACK ON mode.

Signed-off-by: Surbhi Kakarya &lt;surbhi.kakarya@amd.com&gt;
Reviewed-by: Shaoyun Liu &lt;shaoyun.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Use function for IP version check</title>
<updated>2023-09-20T16:23:28Z</updated>
<author>
<name>Lijo Lazar</name>
<email>lijo.lazar@amd.com</email>
</author>
<published>2023-09-11T08:18:11Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=4e8303cf2c4dd27374a16a8881ec1a1cd5baf86f'/>
<id>urn:sha1:4e8303cf2c4dd27374a16a8881ec1a1cd5baf86f</id>
<content type='text'>
Use an inline function for version check. Gives more flexibility to
handle any format changes.

Signed-off-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Clean up errors in amdgpu_virt.c</title>
<updated>2023-08-09T13:43:47Z</updated>
<author>
<name>Ran Sun</name>
<email>sunran001@208suo.com</email>
</author>
<published>2023-08-02T07:31:41Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=baa5ede87568677b6321f9559b7bc2a16acb3f10'/>
<id>urn:sha1:baa5ede87568677b6321f9559b7bc2a16acb3f10</id>
<content type='text'>
Fix the following errors reported by checkpatch:

ERROR: space required before the open parenthesis '('

Signed-off-by: Ran Sun &lt;sunran001@208suo.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: load sdma ucode in the guest machine</title>
<updated>2023-07-25T17:47:26Z</updated>
<author>
<name>YuanShang</name>
<email>YuanShang.Mao@amd.com</email>
</author>
<published>2023-06-30T08:40:28Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=30b59910d9d003424ae1dc327070ad59195c87b2'/>
<id>urn:sha1:30b59910d9d003424ae1dc327070ad59195c87b2</id>
<content type='text'>
[why]
User mode driver need to check the sdma ucode version to
see whether the sdma engine supports a new type of PM4 packet.
In SRIOV, sdma is loaded by the host. And, there is no way
to check the sdma ucode version of CHIP_NAVI12 and
CHIP_SIENNA_CICHLID of the host in the guest machine.

[how]
Load the sdma ucode for CHIP_NAVI12 and CHIP_SIENNA_CICHLID
in the guest machine.

Signed-off-by: YuanShang &lt;YuanShang.Mao@amd.com&gt;
Reviewed-By: Horace Chen &lt;horace.chen@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: set sw state to gfxoff after SR-IOV reset</title>
<updated>2023-07-25T17:35:23Z</updated>
<author>
<name>Horace Chen</name>
<email>horace.chen@amd.com</email>
</author>
<published>2023-07-19T07:55:04Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=83f24a8f0532f6d9fcdbe36e438f00a1a082fcd4'/>
<id>urn:sha1:83f24a8f0532f6d9fcdbe36e438f00a1a082fcd4</id>
<content type='text'>
[Why]
Current SR-IOV will not set GC to off state, while it is a real
GC hard reset. Whthout GFX off flag, driver may do gfxhub invalidation
before firmware load and gfxhub gart enable. This operation may cause
CP to become busy because GC is not in the right state for invalidation.

[How]
Add a function for SR-IOV to clean up some sw state before recover. Set
adev-&gt;gfx.is_poweron to false to prevent gfxhub invalidation before gfx
firmware autoload complete.

Signed-off-by: Horace Chen &lt;horace.chen@amd.com&gt;
Reviewed-by: HaiJun Chang &lt;HaiJun.Chang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add RLCG interface driver implementation for gfx v9.4.3 (v3)</title>
<updated>2023-07-18T15:16:41Z</updated>
<author>
<name>Victor Lu</name>
<email>victorchengchi.lu@amd.com</email>
</author>
<published>2023-06-16T15:01:59Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=8ed49dd1d3a7448744d57e1da2062b074cba2e49'/>
<id>urn:sha1:8ed49dd1d3a7448744d57e1da2062b074cba2e49</id>
<content type='text'>
Add RLCG interface support for gfx v9.4.3 and multiple XCCs.
Do not enable it yet.

v2: Fix amdgpu_rlcg_reg_access_ctrl init, add support for multiple XCCs
    in amdgpu_mm_wreg_mmio_rlc

v3: Use GET_INST() when indexing amdgpu_rlcg_reg_access_ctrl

Signed-off-by: Victor Lu &lt;victorchengchi.lu@amd.com&gt;
Reviewed-by: Zhigang Luo &lt;zhigang.luo@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: make mcbp a per device setting</title>
<updated>2023-06-30T17:12:14Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2023-06-16T20:49:04Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=02ff519e99fc90f6c9aed50def1b6d65e20c1875'/>
<id>urn:sha1:02ff519e99fc90f6c9aed50def1b6d65e20c1875</id>
<content type='text'>
So we can selectively enable it on certain devices.  No
intended functional change.

Reviewed-and-tested-by: Jiadong Zhu &lt;Jiadong.Zhu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
