linux/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h, branch v5.6

drm/amdgpu: provide a generic function interface for reading/writing register by KIQ

2020-01-22T21:34:14Z

Move amdgpu_virt_kiq_rreg/amdgpu_virt_kiq_wreg function to amdgpu_gfx.c, and rename them to amdgpu_kiq_rreg/amdgpu_kiq_wreg.Make it generic and flexible. Signed-off-by: chen gong Reviewed-by: Alex Deucher Reviewed-by: Huang Rui Acked-by: Christian König Signed-off-by: Alex Deucher

drm/amd/powerplay: enable pp one vf mode for vega10

2019-12-11T20:22:07Z

Originally, due to the restriction from PSP and SMU, VF has to send message to hypervisor driver to handle powerplay change which is complicated and redundant. Currently, SMU and PSP can support VF to directly handle powerplay change by itself. Therefore, the old code about the handshake between VF and PF to handle powerplay will be removed and VF will use new the registers below to handshake with SMU. mmMP1_SMN_C2PMSG_101: register to handle SMU message mmMP1_SMN_C2PMSG_102: register to handle SMU parameter mmMP1_SMN_C2PMSG_103: register to handle SMU response v2: remove module parameter pp_one_vf v3: fix the parens v4: forbid vf to change smu feature v5: use hwmon_attributes_visible to skip sepicified hwmon atrribute v6: change skip condition at vega10_copy_table_to_smc Signed-off-by: Yintian Tao Acked-by: Evan Quan Reviewed-by: Kenneth Feng Signed-off-by: Alex Deucher

drm/amdgpu: cleanup vega10 SRIOV code path

2019-08-02T15:17:21Z

we can simplify all those unnecessary function under SRIOV for vega10 since: 1) PSP L1 policy is by force enabled in SRIOV 2) original logic always set all flags which make itself a dummy step besides, 1) the ih_doorbell_range set should also be skipped for VEGA10 SRIOV. 2) the gfx_common registers should also be skipped for VEGA10 SRIOV. Signed-off-by: Monk Liu Reviewed-by: Emily Deng Signed-off-by: Alex Deucher

drm/amdgpu: program for resuming preempted ib

2019-06-21T23:57:40Z

For new submission ib, CE/DE metadata should be programmed to 0; for partially execution ib, CE/DE metadata should be restored. Acked-by: Alex Deucher Reviewed-by: Hawking Zhang Signed-off-by: Jack Xiao Signed-off-by: Alex Deucher

drm/amdgpu: init vega10 SR-IOV reg access mode

2019-05-24T17:20:50Z

Set different register access mode according to the features provided by firmware Signed-off-by: Trigger Huang Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu: support dpm level modification under virtualization v3

2019-04-10T18:53:27Z

Under vega10 virtualuzation, smu ip block will not be added. Therefore, we need add pp clk query and force dpm level function at amdgpu_virt_ops to support the feature. v2: add get_pp_clk existence check and use kzalloc to allocate buf v3: return -ENOMEM for allocation failure and correct the coding style Signed-off-by: Yintian Tao Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amd/amdgpu/sriov: Aligned the definition with libgv

2018-11-19T20:27:42Z

Aligned the amd_sriov_msg_pf2vf_info_header and amd_sriov_msg_pf2vf_info_header's definition with libgv. Signed-off-by: Emily Deng Reviewed-by: Frank.Min Signed-off-by: Alex Deucher

drm/amdgpu: cleanup GMC v9 TLB invalidation

2018-11-05T20:49:40Z

Move the kiq handling into amdgpu_virt.c and drop the fallback. Signed-off-by: Christian König Reviewed-by: Emily Deng Signed-off-by: Alex Deucher

drm/amdgpu: Move csa related code to separate file

2018-11-05T19:21:49Z

In baremetal, also need to reserve csa for preemption. so move the csa related code out of sriov. Reviewed-by: Monk Liu Signed-off-by: Rex Zhu Signed-off-by: Alex Deucher

drm/amdgpu: Refine CSA related functions

2018-11-05T19:21:48Z

There is no functional changes, Use function arguments for SRIOV special variables which is hardcode in those functions. so we can share those functions in baremetal. Reviewed-by: Monk Liu Signed-off-by: Rex Zhu Signed-off-by: Alex Deucher