<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h, branch v6.0</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v6.0</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v6.0'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2022-02-16T22:30:02Z</updated>
<entry>
<title>drm/amdgpu: Fix wait for RLCG command completion</title>
<updated>2022-02-16T22:30:02Z</updated>
<author>
<name>Victor Skvortsov</name>
<email>victor.skvortsov@amd.com</email>
</author>
<published>2022-02-03T21:13:40Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=aa79d3808e8cf1f5fd0f1c20c2e6a6865b5b940c'/>
<id>urn:sha1:aa79d3808e8cf1f5fd0f1c20c2e6a6865b5b940c</id>
<content type='text'>
if (!(tmp &amp; flag)) condition will always evaluate to true
when the flag is 0x0 (AMDGPU_RLCG_GC_WRITE). Instead check
that address bits are cleared to determine whether
the command is complete.

Signed-off-by: Victor Skvortsov &lt;victor.skvortsov@amd.com&gt;
Tested-by: Bokun Zhang &lt;bokun.zhang@amd.com&gt;
Reviewed by: Shaoyun.liu &lt;Shaoyun.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add determine passthrough under arm64</title>
<updated>2022-01-27T20:47:34Z</updated>
<author>
<name>Victor Zhao</name>
<email>Victor.Zhao@amd.com</email>
</author>
<published>2022-01-24T04:13:58Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=039cacd2393971fe11f855118eea6c83c8f506fa'/>
<id>urn:sha1:039cacd2393971fe11f855118eea6c83c8f506fa</id>
<content type='text'>
add determine for passthrough mode under arm64 by reading
CurrentEL register

v2: squash in warning fix (Alex)

Signed-off-by: Victor Zhao &lt;Victor.Zhao@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: retire rlc callbacks sriov_rreg/wreg</title>
<updated>2022-01-25T23:00:33Z</updated>
<author>
<name>Hawking Zhang</name>
<email>Hawking.Zhang@amd.com</email>
</author>
<published>2022-01-17T06:33:23Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=381519dff88845bbe522e7446ec1e32e351c670d'/>
<id>urn:sha1:381519dff88845bbe522e7446ec1e32e351c670d</id>
<content type='text'>
Not needed anymore.

Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Zhou, Peng Ju &lt;PengJu.Zhou@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add helper for rlcg indirect reg access</title>
<updated>2022-01-25T23:00:33Z</updated>
<author>
<name>Hawking Zhang</name>
<email>Hawking.Zhang@amd.com</email>
</author>
<published>2022-01-18T13:44:06Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=5d447e296701484f3df5b31a7a078cbf1e3a9cc9'/>
<id>urn:sha1:5d447e296701484f3df5b31a7a078cbf1e3a9cc9</id>
<content type='text'>
The helper will be used to access registers from sriov
guest in full access time

Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Zhou, Peng Ju &lt;PengJu.Zhou@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add helper to query rlcg reg access flag</title>
<updated>2022-01-25T23:00:33Z</updated>
<author>
<name>Hawking Zhang</name>
<email>Hawking.Zhang@amd.com</email>
</author>
<published>2022-01-18T08:04:02Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=29dbcac82f96d06608f3658aacd3e14efb7ac0cd'/>
<id>urn:sha1:29dbcac82f96d06608f3658aacd3e14efb7ac0cd</id>
<content type='text'>
Query rlc indirect register access approach specified
by sriov host driver per ip blocks

Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Zhou, Peng Ju &lt;PengJu.Zhou@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Separate vf2pf work item init from virt data exchange</title>
<updated>2021-12-16T19:08:20Z</updated>
<author>
<name>Victor Skvortsov</name>
<email>victor.skvortsov@amd.com</email>
</author>
<published>2021-12-16T17:01:45Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=892deb48269c65376f3eeb5b4c032ff2c2979bd7'/>
<id>urn:sha1:892deb48269c65376f3eeb5b4c032ff2c2979bd7</id>
<content type='text'>
We want to be able to call virt data exchange conditionally
after gmc sw init to reserve bad pages as early as possible.
Since this is a conditional call, we will need
to call it again unconditionally later in the init sequence.

Refactor the data exchange function so it can be
called multiple times without re-initializing the work item.

v2: Cleaned up the code. Kept the original call to init_exchange_data()
inside early init to initialize the work item, afterwards call
exchange_data() when needed.

Signed-off-by: Victor Skvortsov &lt;victor.skvortsov@amd.com&gt;
Reviewed By: Shaoyun.liu &lt;Shaoyun.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Complete multimedia bandwidth interface</title>
<updated>2021-05-20T02:29:58Z</updated>
<author>
<name>Bokun Zhang</name>
<email>bokun.zhang@amd.com</email>
</author>
<published>2021-05-13T05:17:54Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=ed9d205363c3ec786126e46568e9e9aadaf0cb93'/>
<id>urn:sha1:ed9d205363c3ec786126e46568e9e9aadaf0cb93</id>
<content type='text'>
- Update SRIOV PF2VF header with latest revision

- Extend existing function in amdgpu_virt.c to read MM bandwidth config
  from PF2VF message

- Add SRIOV Sienna Cichlid codec array and update the bandwidth with
  PF2VF message

v2: squash in removal of unused variable (Alex)

Signed-off-by: Bokun Zhang &lt;bokun.zhang@amd.com&gt;
Reviewed-by: Monk liu &lt;monk.liu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: indirect register access for nv12 sriov</title>
<updated>2021-04-09T20:50:13Z</updated>
<author>
<name>Peng Ju Zhou</name>
<email>PengJu.Zhou@amd.com</email>
</author>
<published>2021-03-30T10:27:15Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=5d23851029b78fb6d6d56a40300676d49a0ce609'/>
<id>urn:sha1:5d23851029b78fb6d6d56a40300676d49a0ce609</id>
<content type='text'>
using the control bits got from host to control registers access.

Signed-off-by: Peng Ju Zhou &lt;PengJu.Zhou@amd.com&gt;
Reviewed-by: Emily.Deng &lt;Emily.Deng@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: indirect register access for nv12 sriov</title>
<updated>2021-04-09T20:50:06Z</updated>
<author>
<name>Peng Ju Zhou</name>
<email>PengJu.Zhou@amd.com</email>
</author>
<published>2021-03-31T03:19:02Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=8b8a162da820d48bb94261ae4684f2c839ce148c'/>
<id>urn:sha1:8b8a162da820d48bb94261ae4684f2c839ce148c</id>
<content type='text'>
unify host driver and guest driver indirect access
control bits names

Signed-off-by: Peng Ju Zhou &lt;PengJu.Zhou@amd.com&gt;
Reviewed-by: Emily.Deng &lt;Emily.Deng@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add new PF2VF flags for VF register access method</title>
<updated>2021-04-09T20:49:22Z</updated>
<author>
<name>Rohit Khaire</name>
<email>rohit.khaire@amd.com</email>
</author>
<published>2021-03-29T19:40:13Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=4d675e1eb863596811f005802116a3c4afbfa95a'/>
<id>urn:sha1:4d675e1eb863596811f005802116a3c4afbfa95a</id>
<content type='text'>
Add 3 sub flags to notify guest for indirect reg access of
gc, mmhub and ih

The host sets these flags depending on L1 RAP version,
asic and other scenarios. These flags ensure that
there is compatibility between different guest/host/vbios versions.

Signed-off-by: Rohit Khaire &lt;rohit.khaire@amd.com&gt;
Reviewed-by: Monk Liu &lt;monk.liu@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Acked-by: Luben Tuikov &lt;luben.tuikov@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
