<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c, branch v5.7</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.7</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.7'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2020-03-19T04:03:04Z</updated>
<entry>
<title>drm/amdgpu: miss PRT case when bo update</title>
<updated>2020-03-19T04:03:04Z</updated>
<author>
<name>Yintian Tao</name>
<email>yttao@amd.com</email>
</author>
<published>2020-03-16T07:45:58Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=31d0271d450f307f862d47d459f3ddf5b9c9e876'/>
<id>urn:sha1:31d0271d450f307f862d47d459f3ddf5b9c9e876</id>
<content type='text'>
Originally, only the PTE valid is taken in consider.
The PRT case is missied when bo update which raise problem.
We need add condition for PRT case.

v2: add PRT condition for amdgpu_vm_bo_update_mapping, too
v3: fix one typo error

Signed-off-by: Yintian Tao &lt;yttao@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm_amdgpu: Add job fence to resv conditionally</title>
<updated>2020-03-16T20:21:32Z</updated>
<author>
<name>xinhui pan</name>
<email>xinhui.pan@amd.com</email>
</author>
<published>2020-03-16T03:45:14Z</published>
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<id>urn:sha1:57210c19e4ee34f1e1986a05f6626fac55ba271f</id>
<content type='text'>
Job fence on page table should be a shared one, so add it to the root
page talbe bo resv.
last_delayed field is not needed anymore. so remove it.

Cc: Christian König &lt;christian.koenig@amd.com&gt;
Cc: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Suggested-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: xinhui pan &lt;xinhui.pan@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Update SPM_VMID with the job's vmid when application reserves the vmid</title>
<updated>2020-03-06T19:32:16Z</updated>
<author>
<name>Jacob He</name>
<email>jacob.he@amd.com</email>
</author>
<published>2020-02-28T12:24:41Z</published>
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<id>urn:sha1:5e208eb62bb308ebf70fd03145c54215d72e7ba6</id>
<content type='text'>
SPM access the video memory according to SPM_VMID. It should be updated
with the job's vmid right before the job is scheduled. SPM_VMID is a
global resource

Signed-off-by: Jacob He &lt;jacob.he@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add VM update fences back to the root PD v2</title>
<updated>2020-02-26T19:17:33Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2020-02-19T14:15:22Z</published>
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<id>urn:sha1:42e5fee65e918f16b178ea242b6a96234411cc53</id>
<content type='text'>
Add update fences to the root PD while mapping BOs.

Otherwise PDs freed during the mapping won't wait for
updates to finish and can cause corruptions.

v2: rebased on drm-misc-next

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Fixes: 90b69cdc5f159 drm/amdgpu: stop adding VM updates fences to the resv obj
Reviewed-by: xinhui pan &lt;xinhui.pan@amd.com&gt;
Tested-by: Luben Tuikov &lt;luben.tuikov@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Do not move root PT bo to relocated list</title>
<updated>2020-02-11T16:51:38Z</updated>
<author>
<name>xinhui pan</name>
<email>xinhui.pan@amd.com</email>
</author>
<published>2020-02-11T01:38:18Z</published>
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<id>urn:sha1:a6605c43f986f860947a645516e906512ad99f62</id>
<content type='text'>
As root PD has no parent, we just need move its status to idle.

Suggested-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: xinhui pan &lt;xinhui.pan@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
CC: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: rework synchronization of VM updates v4</title>
<updated>2020-02-05T04:30:39Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2020-01-23T13:49:45Z</published>
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<id>urn:sha1:9f3cc18d19b7b791b8f59bcae51f88e759f73146</id>
<content type='text'>
If provided we only sync to the BOs reservation
object and no longer to the root PD.

v2: update comment, cleanup amdgpu_bo_sync_wait_resv
v3: use correct reservation object while clearing
v4: fix typo in amdgpu_bo_sync_wait_resv

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Tested-by: Tom St Denis &lt;tom.stdenis@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: allow higher level PD invalidations</title>
<updated>2020-02-05T04:30:39Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2020-01-22T12:41:02Z</published>
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<id>urn:sha1:fe6796ac127a8d6d45e95d9d5fd520ea6b74553f</id>
<content type='text'>
Allow partial invalidation on unallocated PDs. This is useful when we
need to silence faults to stop interrupt floods on Vega.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Tested-by: Tom St Denis &lt;tom.stdenis@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: return EINVAL instead of ENOENT in the VM code</title>
<updated>2020-02-05T04:30:39Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2020-01-22T12:38:43Z</published>
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<id>urn:sha1:7d28efe0c3c0d14d8c04e15efe8d3d59f12c1049</id>
<content type='text'>
That we can't find a PD above the root is expected can only happen if
we try to update a larger range than actually managed by the VM.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Tested-by: Tom St Denis &lt;tom.stdenis@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fix parentheses in amdgpu_vm_update_ptes</title>
<updated>2020-02-05T04:30:39Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2020-01-30T12:09:07Z</published>
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<id>urn:sha1:bfcd6c69e4c3f73f2f92b997983537f9a3ac3b29</id>
<content type='text'>
For the root PD mask can be 0xffffffff as well which would
overrun to 0 if we don't cast it before we add one.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Tested-by: Tom St Denis &lt;tom.stdenis@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: make sure to never allocate PDs/PTs for invalidations</title>
<updated>2020-02-05T04:30:39Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2019-12-18T14:45:17Z</published>
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<id>urn:sha1:46cf5f7626c708fe914142dddbf0d6dea94e3801</id>
<content type='text'>
Make sure that we never allocate a page table for an invalidation operation.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
