<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c, branch v6.19</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v6.19</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v6.19'/>
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<updated>2026-01-14T20:06:51Z</updated>
<entry>
<title>Revert "drm/amdgpu: don't attach the tlb fence for SI"</title>
<updated>2026-01-14T20:06:51Z</updated>
<author>
<name>Prike Liang</name>
<email>Prike.Liang@amd.com</email>
</author>
<published>2026-01-09T08:15:11Z</published>
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<id>urn:sha1:808c2052f046d730a588f7b92b04a12f64970853</id>
<content type='text'>
This reverts commit 820b3d376e8a102c6aeab737ec6edebbbb710e04.

It’s better to validate VM TLB flushes in the flush‑TLB backend
rather than in the generic VM layer.

Reverting this patch depends on
commit fa7c231fc2b0 ("drm/amdgpu: validate the flush_gpu_tlb_pasid()")
being present in the tree.

Signed-off-by: Prike Liang &lt;Prike.Liang@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
(cherry picked from commit 9163fe4d790fb4e16d6b0e23f55b43cddd3d4a65)
</content>
</entry>
<entry>
<title>drm/amdgpu: don't attach the tlb fence for SI</title>
<updated>2025-12-08T20:24:16Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2025-12-02T19:24:03Z</published>
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<id>urn:sha1:eb296c09805ee37dd4ea520a7fb3ec157c31090f</id>
<content type='text'>
SI hardware doesn't support pasids, user mode queues, or
KIQ/MES so there is no need for this.  Doing so results in
a segfault as these callbacks are non-existent for SI.

Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4744
Fixes: f3854e04b708 ("drm/amdgpu: attach tlb fence to the PTs update")
Reviewed-by: Timur Kristóf &lt;timur.kristof@gmail.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
(cherry picked from commit 820b3d376e8a102c6aeab737ec6edebbbb710e04)
</content>
</entry>
<entry>
<title>drm/amdgpu: Forward VMID reservation errors</title>
<updated>2025-12-02T16:02:07Z</updated>
<author>
<name>Natalie Vock</name>
<email>natalie.vock@gmx.de</email>
</author>
<published>2025-12-01T17:52:38Z</published>
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<id>urn:sha1:8defb4f081a5feccc3ea8372d0c7af3522124e1f</id>
<content type='text'>
Otherwise userspace may be fooled into believing it has a reserved VMID
when in reality it doesn't, ultimately leading to GPU hangs when SPM is
used.

Fixes: 80e709ee6ecc ("drm/amdgpu: add option params to enforce process isolation between graphics and compute")
Cc: stable@vger.kernel.org
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Natalie Vock &lt;natalie.vock@gmx.de&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: attach tlb fence to the PTs update</title>
<updated>2025-11-26T16:50:43Z</updated>
<author>
<name>Prike Liang</name>
<email>Prike.Liang@amd.com</email>
</author>
<published>2025-10-31T09:02:51Z</published>
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<id>urn:sha1:f3854e04b708d73276c4488231a8bd66d30b4671</id>
<content type='text'>
Ensure the userq TLB flush is emitted only after
the VM update finishes and the PT BOs have been
annotated with bookkeeping fences.

Suggested-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Prike Liang &lt;Prike.Liang@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/vm: Check PRT uAPI flag instead of PTE flag</title>
<updated>2025-11-19T22:34:15Z</updated>
<author>
<name>Timur Kristóf</name>
<email>timur.kristof@gmail.com</email>
</author>
<published>2025-11-19T09:25:42Z</published>
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<id>urn:sha1:8feeab26c80635b802f72b3ed986c693ff8f3212</id>
<content type='text'>
This fixes sparse mappings (aka. partially resident textures).

Check the correct flags.
Since a recent refactor, the code works with uAPI flags (for
mapping buffer objects), and not PTE (page table entry) flags.

Fixes: 6716a823d18d ("drm/amdgpu: rework how PTE flags are generated v3")
Signed-off-by: Timur Kristóf &lt;timur.kristof@gmail.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: avoid memory allocation in the critical code path v3</title>
<updated>2025-11-14T16:27:46Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2025-10-29T14:36:32Z</published>
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<id>urn:sha1:20459c098d688971237e56e30263ddce467c8c9b</id>
<content type='text'>
When we run out of VMIDs we need to wait for some to become available.
Previously we were using a dma_fence_array for that, but this means that
we have to allocate memory.

Instead just wait for the first not signaled fence from the least recently
used VMID to signal. That is not as efficient since we end up in this
function multiple times again, but allocating memory can easily fail or
deadlock if we have to wait for memory to become available.

v2: remove now unused VM manager fields
v3: fix dma_fence reference

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4258
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fix possible fence leaks from job structure</title>
<updated>2025-11-04T16:53:59Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2025-10-22T21:11:38Z</published>
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<id>urn:sha1:f903b85ed0f14fc412d8a781d3fcc0c023dfcd7c</id>
<content type='text'>
If we don't end up initializing the fences, free them when
we free the job.  We can't set the hw_fence to NULL after
emitting it because we need it in the cleanup path for the
submit direct case.

v2: take a reference to the fences if we emit them
v3: handle non-job fence in error paths

Fixes: db36632ea51e ("drm/amdgpu: clean up and unify hw fence handling")
Reviewed-by: Jesse Zhang &lt;Jesse.Zhang@amd.com&gt; (v1)
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: grab a BO reference in vm_lock_done_list.</title>
<updated>2025-11-04T16:53:21Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2025-10-31T08:21:36Z</published>
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<id>urn:sha1:c72d41a8f3090c2ecc12afdde1bcf9ed726157ce</id>
<content type='text'>
Otherwise it is possible that between dropping the status lock and
locking the BO that the BO is freed up.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Sunil Khatri &lt;sunil.khatri@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: clean up and unify hw fence handling</title>
<updated>2025-10-13T18:14:35Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2025-08-27T15:34:14Z</published>
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<id>urn:sha1:db36632ea51e8b02dd637d291c755899b20a5a31</id>
<content type='text'>
Decouple the amdgpu fence from the amdgpu_job structure.
This lets us clean up the separate fence ops for the embedded
fence and other fences.  This also allows us to allocate the
vm fence up front when we allocate the job.

v2: Additional cleanup suggested by Christian
v3: Additional cleanups suggested by Christian
v4: Additional cleanups suggested by David and
    vm fence fix
v5: cast seqno (David)

Cc: David.Wu3@amd.com
Cc: christian.koenig@amd.com
Tested-by: David (Ming Qiang) Wu &lt;David.Wu3@amd.com&gt;
Reviewed-by: David (Ming Qiang) Wu &lt;David.Wu3@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: validate userq va for GEM unmap</title>
<updated>2025-10-13T18:14:34Z</updated>
<author>
<name>Prike Liang</name>
<email>Prike.Liang@amd.com</email>
</author>
<published>2025-09-19T07:14:41Z</published>
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<id>urn:sha1:2e7ceac0ea4192e25936c2186e1c44a550f6d96d</id>
<content type='text'>
When a user unmaps a userq VA, the driver must ensure
the queue has no in-flight jobs. If there is pending work,
the kernel should wait for the attached eviction (bookkeeping)
fence to signal before deleting the mapping.

Suggested-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Prike Liang &lt;Prike.Liang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
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