<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h, branch v4.15</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v4.15</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v4.15'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2017-11-13T19:36:40Z</updated>
<entry>
<title>drm/amdgpu: make AMDGPU_VA_RESERVED_SIZE 64bit</title>
<updated>2017-11-13T19:36:40Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2017-11-06T14:25:37Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=ff4cd38943199348a53f980709e16f0bc5c0b8c9'/>
<id>urn:sha1:ff4cd38943199348a53f980709e16f0bc5c0b8c9</id>
<content type='text'>
Even when it's a small handle it as 64bit value as well.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Set the correct value for PDEs/PTEs of ATC memory on Raven</title>
<updated>2017-10-09T20:30:16Z</updated>
<author>
<name>Yong Zhao</name>
<email>Yong.Zhao@amd.com</email>
</author>
<published>2017-08-31T19:55:00Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=6d16dac85c081825af58111023428c43d1da7e1a'/>
<id>urn:sha1:6d16dac85c081825af58111023428c43d1da7e1a</id>
<content type='text'>
Without the additional bits set in PDEs/PTEs, the ATC memory access
would have failed on Raven.

Signed-off-by: Yong Zhao &lt;yong.zhao@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'drm-next-4.15' of git://people.freedesktop.org/~agd5f/linux into drm-next</title>
<updated>2017-10-09T01:00:16Z</updated>
<author>
<name>Dave Airlie</name>
<email>airlied@redhat.com</email>
</author>
<published>2017-10-09T01:00:16Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=bb7a9c8d712f37385a706a594d6edf6e6d2669d0'/>
<id>urn:sha1:bb7a9c8d712f37385a706a594d6edf6e6d2669d0</id>
<content type='text'>
More new stuff for 4.15. Highlights:
- Add clock query interface for raven
- Add new FENCE_TO_HANDLE ioctl
- UVD video encode ring support on polaris
- transparent huge page DMA support
- deadlock fixes
- compute pipe lru tweaks
- powerplay cleanups and regression fixes
- fix duplicate symbol issue with radeon and amdgpu
- misc bug fixes

* 'drm-next-4.15' of git://people.freedesktop.org/~agd5f/linux: (72 commits)
  drm/radeon/dp: make radeon_dp_get_dp_link_config static
  drm/radeon: move ci_send_msg_to_smc to where it's used
  drm/amd/sched: fix deadlock caused by unsignaled fences of deleted jobs
  drm/amd/sched: NULL out the s_fence field after run_job
  drm/amd/sched: move adding finish callback to amd_sched_job_begin
  drm/amd/sched: fix an outdated comment
  drm/amd/sched: rename amd_sched_entity_pop_job
  drm/amdgpu: minor coding style fix
  drm/ttm: add transparent huge page support for DMA allocations v2
  drm/ttm: add support for different pool sizes
  drm/ttm: remove unsued options from ttm_mem_global_alloc_page
  drm/amdgpu: add uvd enc irq
  drm/amdgpu: add uvd enc ib test
  drm/amdgpu: add uvd enc ring test
  drm/amdgpu: add uvd enc vm functions (v2)
  drm/amdgpu: add uvd enc into run queue
  drm/amdgpu: add uvd enc rings
  drm/amdgpu: add new uvd enc ring methods
  drm/amdgpu: add uvd enc command in header
  drm/amdgpu: add uvd enc registers in header
  ...
</content>
</entry>
<entry>
<title>drm/amdgpu: Handle GPUVM fault storms</title>
<updated>2017-09-28T20:03:30Z</updated>
<author>
<name>Felix Kuehling</name>
<email>Felix.Kuehling@amd.com</email>
</author>
<published>2017-09-21T20:26:41Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=c98171ccf6580407d07a3b5dc8188ce9e1f4f7ca'/>
<id>urn:sha1:c98171ccf6580407d07a3b5dc8188ce9e1f4f7ca</id>
<content type='text'>
When many wavefronts cause VM faults at the same time, it can
overwhelm the interrupt handler and cause IH ring overflows before
the driver can notify or kill the faulting application.

As a workaround I'm introducing limited per-VM fault credit. After
that number of VM faults have occurred, further VM faults are
filtered out at the prescreen stage of processing.

This depends on the PASID in the interrupt packet, so it currently
only works for KFD contexts.

Signed-off-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'drm-next-4.15' of git://people.freedesktop.org/~agd5f/linux into drm-next</title>
<updated>2017-09-27T22:37:02Z</updated>
<author>
<name>Dave Airlie</name>
<email>airlied@redhat.com</email>
</author>
<published>2017-09-27T22:37:02Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=754270c7c56292e97d0eff924a5d5d83f92add07'/>
<id>urn:sha1:754270c7c56292e97d0eff924a5d5d83f92add07</id>
<content type='text'>
First feature pull for 4.15.  Highlights:
- Per VM BO support
- Lots of powerplay cleanups
- Powerplay support for CI
- pasid mgr for kfd
- interrupt infrastructure for recoverable page faults
- SR-IOV fixes
- initial GPU reset for vega10
- prime mmap support
- ttm page table debugging improvements
- lots of bug fixes

* 'drm-next-4.15' of git://people.freedesktop.org/~agd5f/linux: (232 commits)
  drm/amdgpu: clarify license in amdgpu_trace_points.c
  drm/amdgpu: Add gem_prime_mmap support
  drm/amd/powerplay: delete dead code in smumgr
  drm/amd/powerplay: delete SMUM_FIELD_MASK
  drm/amd/powerplay: delete SMUM_WAIT_INDIRECT_FIELD
  drm/amd/powerplay: delete SMUM_READ_FIELD
  drm/amd/powerplay: delete SMUM_SET_FIELD
  drm/amd/powerplay: delete SMUM_READ_VFPF_INDIRECT_FIELD
  drm/amd/powerplay: delete SMUM_WRITE_VFPF_INDIRECT_FIELD
  drm/amd/powerplay: delete SMUM_WRITE_FIELD
  drm/amd/powerplay: delete SMU_WRITE_INDIRECT_FIELD
  drm/amd/powerplay: move macros to hwmgr.h
  drm/amd/powerplay: move PHM_WAIT_VFPF_INDIRECT_FIELD to hwmgr.h
  drm/amd/powerplay: move SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL to hwmgr.h
  drm/amd/powerplay: move SMUM_WAIT_INDIRECT_FIELD_UNEQUAL to hwmgr.h
  drm/amd/powerplay: add new helper functions in hwmgr.h
  drm/amd/powerplay: use SMU_IND_INDEX/DATA_11 pair
  drm/amd/powerplay: refine powerplay code.
  drm/amd/powerplay: delete dead code in hwmgr.h
  drm/amd/powerplay: refine interface in struct pp_smumgr_func
  ...
</content>
</entry>
<entry>
<title>drm/amdgpu: Track pending retry faults in IH and VM (v2)</title>
<updated>2017-09-26T18:53:20Z</updated>
<author>
<name>Felix Kuehling</name>
<email>Felix.Kuehling@amd.com</email>
</author>
<published>2017-08-26T06:43:06Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=a2f14820e3493145c25095873d4a510a1b25efdc'/>
<id>urn:sha1:a2f14820e3493145c25095873d4a510a1b25efdc</id>
<content type='text'>
IH tracks pending retry faults in a hash table for fast lookup in
interrupt context. Each VM has a short FIFO of pending VM faults for
processing in a bottom half.

The IH prescreening stage adds retry faults and filters out repeated
retry interrupts to minimize the impact of interrupt storms.

It's the VM's responsibility remove pending faults once they are
handled. For now this is only done when the VM is destroyed.

v2:
- Made the hash table smaller and the FIFO longer. I never want the
  FIFO to fill up, because that would make prescreen take longer.
  128 pending page faults should be enough to keep migrations busy.

Signed-off-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt; (v1)
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add PASID management</title>
<updated>2017-09-26T17:07:02Z</updated>
<author>
<name>Felix Kuehling</name>
<email>Felix.Kuehling@amd.com</email>
</author>
<published>2017-08-26T00:40:26Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=02208441cc3a5110191996bb129db39ff10e7395'/>
<id>urn:sha1:02208441cc3a5110191996bb129db39ff10e7395</id>
<content type='text'>
Allows assigning a PASID to a VM for identifying VMs involved in page
faults. The global PASID manager is also exported in the KFD
interface so that AMDGPU and KFD can share the PASID space.

PASIDs of different sizes can be requested. On APUs, the PASID size
is deterined by the capabilities of the IOMMU. So KFD must be able
to allocate PASIDs in a smaller range.

Signed-off-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Oded Gabbay &lt;oded.gabbay@gmail.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fix amdgpu_vm_handle_moved as well v2</title>
<updated>2017-09-13T16:10:06Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2017-09-11T14:54:59Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=4e55eb3879fea6d8c7d414cebaa5bff1da58b4a1'/>
<id>urn:sha1:4e55eb3879fea6d8c7d414cebaa5bff1da58b4a1</id>
<content type='text'>
There is no guarantee that the last BO_VA actually needed an update.

Additional to that all command submissions must wait for moved BOs to
be cleared, not just the first one.

v2: Don't overwrite any newer fence.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fix VM sync with always valid BOs v2</title>
<updated>2017-09-12T18:30:39Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2017-09-08T12:09:41Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=d5884513a31df072879c89c80306d544467ee770'/>
<id>urn:sha1:d5884513a31df072879c89c80306d544467ee770</id>
<content type='text'>
All users of a VM must always wait for updates with always
valid BOs to be completed.

v2: remove debugging leftovers, rename struct member

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Roger He &lt;Hongbo.He@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: rework amdgpu_cs_find_mapping</title>
<updated>2017-09-12T18:27:48Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2017-09-06T14:55:16Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=aebc5e6f50f770ec9392c3ca804f18b30797dfa7'/>
<id>urn:sha1:aebc5e6f50f770ec9392c3ca804f18b30797dfa7</id>
<content type='text'>
Use the VM instead of the BO list to find the BO for a virtual address.

This fixes UVD/VCE in physical mode with VM local BOs.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Acked-by: Leo Liu &lt;leo.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
