<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h, branch v5.10</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.10</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.10'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2020-10-26T21:11:31Z</updated>
<entry>
<title>drm/amdgpu: increase the reserved VM size to 2MB</title>
<updated>2020-10-26T21:11:31Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2020-10-12T11:09:36Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=55bb919be4e4973cd037a04f527ecc6686800437'/>
<id>urn:sha1:55bb919be4e4973cd037a04f527ecc6686800437</id>
<content type='text'>
Ideally this should be a multiple of the VM block size.
2MB should at least fit for Vega/Navi.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Madhav Chauhan &lt;madhav.chauhan@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>Merge tag 'drm-next-2020-10-15' of git://anongit.freedesktop.org/drm/drm</title>
<updated>2020-10-15T17:46:16Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2020-10-15T17:46:16Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=93b694d096cc10994c817730d4d50288f9ae3d66'/>
<id>urn:sha1:93b694d096cc10994c817730d4d50288f9ae3d66</id>
<content type='text'>
Pull drm updates from Dave Airlie:
 "Not a major amount of change, the i915 trees got split into display
  and gt trees to better facilitate higher level review, and there's a
  major refactoring of i915 GEM locking to use more core kernel concepts
  (like ww-mutexes). msm gets per-process pagetables, older AMD SI cards
  get DC support, nouveau got a bump in displayport support with common
  code extraction from i915.

  Outside of drm this contains a couple of patches for hexint
  moduleparams which you've acked, and a virtio common code tree that
  you should also get via it's regular path.

  New driver:
   - Cadence MHDP8546 DisplayPort bridge driver

  core:
   - cross-driver scatterlist cleanups
   - devm_drm conversions
   - remove drm_dev_init
   - devm_drm_dev_alloc conversion

  ttm:
   - lots of refactoring and cleanups

  bridges:
   - chained bridge support in more drivers

  panel:
   - misc new panels

  scheduler:
   - cleanup priority levels

  displayport:
   - refactor i915 code into helpers for nouveau

  i915:
   - split into display and GT trees
   - WW locking refactoring in GEM
   - execbuf2 extension mechanism
   - syncobj timeline support
   - GEN 12 HOBL display powersaving
   - Rocket Lake display additions
   - Disable FBC on Tigerlake
   - Tigerlake Type-C + DP improvements
   - Hotplug interrupt refactoring

  amdgpu:
   - Sienna Cichlid updates
   - Navy Flounder updates
   - DCE6 (SI) support for DC
   - Plane rotation enabled
   - TMZ state info ioctl
   - PCIe DPC recovery support
   - DC interrupt handling refactor
   - OLED panel fixes

  amdkfd:
   - add SMI events for thermal throttling
   - SMI interface events ioctl update
   - process eviction counters

  radeon:
   - move to dma_ for allocations
   - expose sclk via sysfs

  msm:
   - DSI support for sm8150/sm8250
   - per-process GPU pagetable support
   - Displayport support

  mediatek:
   - move HDMI phy driver to PHY
   - convert mtk-dpi to bridge API
   - disable mt2701 tmds

  tegra:
   - bridge support

  exynos:
   - misc cleanups

  vc4:
   - dual display cleanups

  ast:
   - cleanups

  gma500:
   - conversion to GPIOd API

  hisilicon:
   - misc reworks

  ingenic:
   - clock handling and format improvements

  mcde:
   - DSI support

  mgag200:
   - desktop g200 support

  mxsfb:
   - i.MX7 + i.MX8M
   - alpha plane support

  panfrost:
   - devfreq support
   - amlogic SoC support

  ps8640:
   - EDID from eDP retrieval

  tidss:
   - AM65xx YUV workaround

  virtio:
   - virtio-gpu exported resources

  rcar-du:
   - R8A7742, R8A774E1 and R8A77961 support
   - YUV planar format fixes
   - non-visible plane handling
   - VSP device reference count fix
   - Kconfig fix to avoid displaying disabled options in .config"

* tag 'drm-next-2020-10-15' of git://anongit.freedesktop.org/drm/drm: (1494 commits)
  drm/ingenic: Fix bad revert
  drm/amdgpu: Fix invalid number of character '{' in amdgpu_acpi_init
  drm/amdgpu: Remove warning for virtual_display
  drm/amdgpu: kfd_initialized can be static
  drm/amd/pm: setup APU dpm clock table in SMU HW initialization
  drm/amdgpu: prevent spurious warning
  drm/amdgpu/swsmu: fix ARC build errors
  drm/amd/display: Fix OPTC_DATA_FORMAT programming
  drm/amd/display: Don't allow pstate if no support in blank
  drm/panfrost: increase readl_relaxed_poll_timeout values
  MAINTAINERS: Update entry for st7703 driver after the rename
  Revert "gpu/drm: ingenic: Add option to mmap GEM buffers cached"
  drm/amd/display: HDMI remote sink need mode validation for Linux
  drm/amd/display: Change to correct unit on audio rate
  drm/amd/display: Avoid set zero in the requested clk
  drm/amdgpu: align frag_end to covered address space
  drm/amdgpu: fix NULL pointer dereference for Renoir
  drm/vmwgfx: fix regression in thp code due to ttm init refactor.
  drm/amdgpu/swsmu: add interrupt work handler for smu11 parts
  drm/amdgpu/swsmu: add interrupt work function
  ...
</content>
</entry>
<entry>
<title>drm/amd: fix typoes in comments</title>
<updated>2020-09-22T21:37:38Z</updated>
<author>
<name>Bernard Zhao</name>
<email>bernard@vivo.com</email>
</author>
<published>2020-09-22T12:54:18Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=f349f772b05cafc5ab551f645e9051bcdae8ec86'/>
<id>urn:sha1:f349f772b05cafc5ab551f645e9051bcdae8ec86</id>
<content type='text'>
Change the comment typo: "programm" -&gt; "program".

Signed-off-by: Bernard Zhao &lt;bernard@vivo.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm, iommu: Change type of pasid to u32</title>
<updated>2020-09-17T17:21:16Z</updated>
<author>
<name>Fenghua Yu</name>
<email>fenghua.yu@intel.com</email>
</author>
<published>2020-09-15T16:30:05Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=c7b6bac9c72c5fcbd6e9e12545bd3022c7f21860'/>
<id>urn:sha1:c7b6bac9c72c5fcbd6e9e12545bd3022c7f21860</id>
<content type='text'>
PASID is defined as a few different types in iommu including "int",
"u32", and "unsigned int". To be consistent and to match with uapi
definitions, define PASID and its variations (e.g. max PASID) as "u32".
"u32" is also shorter and a little more explicit than "unsigned int".

No PASID type change in uapi although it defines PASID as __u64 in
some places.

Suggested-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Signed-off-by: Fenghua Yu &lt;fenghua.yu@intel.com&gt;
Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
Reviewed-by: Tony Luck &lt;tony.luck@intel.com&gt;
Reviewed-by: Lu Baolu &lt;baolu.lu@linux.intel.com&gt;
Acked-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Acked-by: Joerg Roedel &lt;jroedel@suse.de&gt;
Link: https://lkml.kernel.org/r/1600187413-163670-2-git-send-email-fenghua.yu@intel.com
</content>
</entry>
<entry>
<title>drm/amdgpu: Clean up KFD VMID assignment</title>
<updated>2020-07-02T16:02:50Z</updated>
<author>
<name>Felix Kuehling</name>
<email>Felix.Kuehling@amd.com</email>
</author>
<published>2020-06-25T03:05:44Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=40111ec2298f442aab299234cd610d90809f58de'/>
<id>urn:sha1:40111ec2298f442aab299234cd610d90809f58de</id>
<content type='text'>
The KFD VMID assignment was hard-coded in a few places. Consolidate that in
a single variable adev-&gt;vm_manager.first_kfd_vmid. The value is still
assigned in gmc-ip-version-specific code.

Signed-off-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add new unlocked flag for PTE updates</title>
<updated>2020-04-28T20:20:30Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2020-04-07T12:54:23Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=9c466bcbda68d73c9ba26e8307b0dff11dd285d8'/>
<id>urn:sha1:9c466bcbda68d73c9ba26e8307b0dff11dd285d8</id>
<content type='text'>
For HMM support we need the ability to invalidate PTEs from
a MM callback where we can't lock the root PD.

Add a new flag to better support this instead of assuming
that all invalidation updates are unlocked.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: rename direct to immediate for VM updates</title>
<updated>2020-04-28T20:20:30Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2020-04-01T10:50:56Z</published>
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<id>urn:sha1:eaad0c3aa978e7ed654e574691b56cc24d2d409a</id>
<content type='text'>
To avoid confusion with direct ring submissions rename bottom
of pipe VM table changes to immediate updates.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: define the TMZ bit for the PTE</title>
<updated>2020-04-28T20:20:28Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2019-08-08T03:31:50Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=c5efd80f48e481946ba201412c7f39b19b39a40b'/>
<id>urn:sha1:c5efd80f48e481946ba201412c7f39b19b39a40b</id>
<content type='text'>
Define the TMZ (encryption) bit in the page table entry (PTE) for
Raven and newer asics.

Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Huang Rui &lt;ray.huang@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fix race between pstate and remote buffer map</title>
<updated>2020-04-22T22:11:46Z</updated>
<author>
<name>Jonathan Kim</name>
<email>jonathan.kim@amd.com</email>
</author>
<published>2020-03-17T19:43:41Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=d84a430d9f7b1ce6baedf1305106d0ae706aca76'/>
<id>urn:sha1:d84a430d9f7b1ce6baedf1305106d0ae706aca76</id>
<content type='text'>
Vega20 arbitrates pstate at hive level and not device level. Last peer to
remote buffer unmap could drop P-State while another process is still
remote buffer mapped.

With this fix, P-States still needs to be disabled for now as SMU bug
was discovered on synchronous P2P transfers.  This should be fixed in the
next FW update.

Signed-off-by: Jonathan Kim &lt;Jonathan.Kim@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm_amdgpu: Add job fence to resv conditionally</title>
<updated>2020-03-16T20:21:32Z</updated>
<author>
<name>xinhui pan</name>
<email>xinhui.pan@amd.com</email>
</author>
<published>2020-03-16T03:45:14Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=57210c19e4ee34f1e1986a05f6626fac55ba271f'/>
<id>urn:sha1:57210c19e4ee34f1e1986a05f6626fac55ba271f</id>
<content type='text'>
Job fence on page table should be a shared one, so add it to the root
page talbe bo resv.
last_delayed field is not needed anymore. so remove it.

Cc: Christian König &lt;christian.koenig@amd.com&gt;
Cc: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Suggested-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: xinhui pan &lt;xinhui.pan@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
