<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h, branch v5.4</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.4</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.4'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2019-07-31T04:19:35Z</updated>
<entry>
<title>drm/amdgpu/gmc10: fix pte mytpe field error for navi14</title>
<updated>2019-07-31T04:19:35Z</updated>
<author>
<name>tiancyin</name>
<email>tianci.yin@amd.com</email>
</author>
<published>2019-07-16T10:25:01Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=5f4814deab509e4d0a52e4a0b016d49a75b2cf7c'/>
<id>urn:sha1:5f4814deab509e4d0a52e4a0b016d49a75b2cf7c</id>
<content type='text'>
navi14 share same PTE format with navi10.

Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: tiancyin &lt;tianci.yin@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add one more mmhub instance for Arcturus (v2)</title>
<updated>2019-07-18T19:18:02Z</updated>
<author>
<name>Le Ma</name>
<email>le.ma@amd.com</email>
</author>
<published>2018-08-31T06:46:47Z</published>
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<id>urn:sha1:c8a6e2a3170064c1f476407139c3dd97d9a9087c</id>
<content type='text'>
v2: set mmhub num under CHIP_ARCTURUS switch case and add one more mmhub id_mgr

Signed-off-by: Le Ma &lt;le.ma@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: rename AMDGPU_GFXHUB/MMHUB macro with hub number</title>
<updated>2019-07-18T19:18:01Z</updated>
<author>
<name>Le Ma</name>
<email>le.ma@amd.com</email>
</author>
<published>2019-07-16T18:29:19Z</published>
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<id>urn:sha1:a2d15ed733365ba2e0e3eb55a83c7a493eaaaa2c</id>
<content type='text'>
The number of GFXHUB/MMHUB may be expanded in later ASICs.

Signed-off-by: Le Ma &lt;le.ma@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: refine the PTE encoding of PRT for navi10</title>
<updated>2019-06-21T02:35:29Z</updated>
<author>
<name>Jack Xiao</name>
<email>Jack.Xiao@amd.com</email>
</author>
<published>2019-02-22T07:34:00Z</published>
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<id>urn:sha1:7f95167ce131674ab77b46e4064f053e6c6f1552</id>
<content type='text'>
Due to GCR change from navi10, the PTE encoding of PRT
needs change VSCTL = 01111 (was 0XX1X).

Signed-off-by: Jack Xiao &lt;Jack.Xiao@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/gmc9: rename AMDGPU_PTE_MTYPE to AMDGPU_PTE_MTYPE_VG10</title>
<updated>2019-06-21T02:35:29Z</updated>
<author>
<name>Hawking Zhang</name>
<email>Hawking.Zhang@amd.com</email>
</author>
<published>2018-06-25T13:03:40Z</published>
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<id>urn:sha1:7596ab68ff7dc13515f0c9dc3803472d75055c60</id>
<content type='text'>
To differentiate the mtypes across asics.

Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: correct pte mtype field for navi</title>
<updated>2019-06-21T02:35:29Z</updated>
<author>
<name>Hawking Zhang</name>
<email>Hawking.Zhang@amd.com</email>
</author>
<published>2019-04-12T23:17:24Z</published>
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<id>urn:sha1:c304b9e51914d6ffe765f35eb39310d35f988a28</id>
<content type='text'>
The MTYPE filed moves from bits 58:57 to 50:48 for NV10
And the size of MTYPE field is now 3bits

Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: provide the page fault queue to the VM code</title>
<updated>2019-04-03T15:00:30Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2019-03-25T15:13:44Z</published>
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<id>urn:sha1:c4229c6e37c203fd99397c1bcfe83a2bc1d30d96</id>
<content type='text'>
We are going to need that for recoverable page faults.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: drop the ib from the VM update parameters</title>
<updated>2019-03-28T03:40:57Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2019-03-21T15:43:39Z</published>
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<id>urn:sha1:110aef572afccc8d18c8d1ad6cb027795ec01cda</id>
<content type='text'>
It is redundant with the job pointer.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: move VM table mapping into the backend as well</title>
<updated>2019-03-28T03:40:50Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2019-03-21T15:34:18Z</published>
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<id>urn:sha1:ecf96b52bf98a22f14bd33c7deee0aad8eb6b569</id>
<content type='text'>
Clean that up further and also fix another case where the BO
wasn't kmapped for CPU based updates.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: XGMI pstate switch initial support</title>
<updated>2019-03-28T03:40:43Z</updated>
<author>
<name>shaoyunl</name>
<email>shaoyun.liu@amd.com</email>
</author>
<published>2019-03-20T20:14:56Z</published>
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<id>urn:sha1:df399b064118bf9a5b9a3faaa67feb1cbb34e9d4</id>
<content type='text'>
Driver vote low to high pstate switch whenever there is an outstanding
XGMI mapping request. Driver vote high to low pstate when all the
outstanding XGMI mapping is terminated.

Signed-off-by: shaoyunl &lt;shaoyun.liu@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
