linux/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h, branch v5.5

drm/amdgpu: add graceful VM fault handling v3

2019-09-16T15:42:55Z

Next step towards HMM support. For now just silence the retry fault and optionally redirect the request to the dummy page. v2: make sure the VM is not destroyed while we handle the fault. v3: fix VM destroy check, cleanup comments Signed-off-by: Christian König Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher

drm/amdgpu: allow direct submission of PDE updates v2

2019-09-16T15:42:55Z

For handling PDE updates directly in the fault handler. v2: fix typo in comment Signed-off-by: Christian König Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher

drm/amdgpu: allow direct submission in the VM backends v2

2019-09-16T15:42:55Z

This allows us to update page tables directly while in a page fault. v2: use direct/delayed entities and still wait for moves Signed-off-by: Christian König Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher

drm/amdgpu: split the VM entity into direct and delayed

2019-09-16T15:42:55Z

For page fault handling we need to use a direct update which can't be blocked by ongoing user CS. Signed-off-by: Christian König Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher

drm/amdgpu: reserve at least 4MB of VRAM for page tables v2

2019-09-13T22:38:47Z

This hopefully helps reduce the contention for page tables. v2: adjust maximum reported VRAM size as well Signed-off-by: Christian König Reviewed-by: Chunming Zhou Signed-off-by: Alex Deucher

drm/amdgpu/gmc10: fix pte mytpe field error for navi14

2019-07-31T04:19:35Z

navi14 share same PTE format with navi10. Reviewed-by: Hawking Zhang Signed-off-by: tiancyin Signed-off-by: Alex Deucher

drm/amdgpu: add one more mmhub instance for Arcturus (v2)

2019-07-18T19:18:02Z

v2: set mmhub num under CHIP_ARCTURUS switch case and add one more mmhub id_mgr Signed-off-by: Le Ma Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher

drm/amdgpu: rename AMDGPU_GFXHUB/MMHUB macro with hub number

2019-07-18T19:18:01Z

The number of GFXHUB/MMHUB may be expanded in later ASICs. Signed-off-by: Le Ma Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher

drm/amdgpu: refine the PTE encoding of PRT for navi10

2019-06-21T02:35:29Z

Due to GCR change from navi10, the PTE encoding of PRT needs change VSCTL = 01111 (was 0XX1X). Signed-off-by: Jack Xiao Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher

drm/amd/gmc9: rename AMDGPU_PTE_MTYPE to AMDGPU_PTE_MTYPE_VG10

2019-06-21T02:35:29Z

To differentiate the mtypes across asics. Signed-off-by: Hawking Zhang Reviewed-by: Alex Deucher Reviewed-by: Christian König Signed-off-by: Alex Deucher