linux/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c, branch v4.14

drm/amdgpu: Support passing amdgpu critical error to host via GPU Mailbox.

2017-07-14T15:05:52Z

This feature works for SRIOV enviroment. For non-SRIOV enviroment, the trans_error function does nothing. The error information includes error_code (16bit), error_flags(16bit) and error_data(64bit). Since there are not many errors, we keep the errors in an array and transfer all errors to Host before amdgpu initialization function (amdgpu_device_init) exit. Signed-off-by: Gavin Wan Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu:only call flr_work under infinite timeout

2017-05-24T21:40:39Z

Signed-off-by: Monk Liu Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu:use job* to replace voluntary

2017-05-24T21:40:38Z

that way we can know which job cause hang and can do per sched reset/recovery instead of all sched. Signed-off-by: Monk Liu Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu:need som change on vega10 mailbox

2017-05-24T21:40:18Z

if sriov gpu reset is invoked by job timeout, it is run in a global work-queue which is very slow and better not call msleep ortherwise it takes long time to get back CPU. so make below changes: 1: Change msleep 1 to mdelay 5 2: Ignore the ack fail from pf after time out, because VF FLR will clear ack, sometime VF FLR is done prior to the beginning of poll_ack so we can ignore this ack TODO: Put job_timedout (and the following gpu reset) in a driver thread, instead of the global work_struct. Signed-off-by: Monk Liu Reviewed-by: Xiangliang Yu Signed-off-by: Alex Deucher

drm/amdgpu/virt: don't check VALID bit for FLR completion message

2017-04-28T21:32:40Z

The interrupt after FLR is missed sometimes due to hardware reason, so guest driver get the notification of FLR completion via polling message. Then host doesn't write VALID bit to avoid sending interrupt, otherwise the completion will be handled twice. So there's a valid message without VALID bit for FLR completion, driver should handle it without checking. Signed-off-by: Pixel Ding Reviewed-by: Xiangliang Yu Signed-off-by: Alex Deucher

drm/amdgpu: switch ih handling to two levels (v3)

2017-03-30T03:53:37Z

Newer asics have a two levels of irq ids now: client id - the IP src id - the interrupt src within the IP v2: integrated Christian's comments. v3: fix rebase fail in SI and CIK Signed-off-by: Alex Deucher Signed-off-by: Ken Wang Reviewed-by: Ken Wang Signed-off-by: Alex Deucher

drm/amdgpu/virt: fix typo

2017-03-30T03:53:16Z

When send messages to hypervior, the messages format should be is idh_request, not idh_event. Signed-off-by: Xiangliang Yu Reviewed-by: Alex Deucher Reviewed-by: Monk Liu Acked-by: Christian KÃ¶nig Signed-off-by: Alex Deucher

drm/amdgpu:RUNTIME flag should clr later

2017-03-30T03:53:12Z

this flag will get cleared by request gpu access Signed-off-by: Monk Liu Reviewed-by: Xiangliang Yu Signed-off-by: Alex Deucher

drm/amdgpu:use work instead of delay-work

2017-03-30T03:53:11Z

no need to use a delay work since we don't know how much time hypervisor takes on FLR, so just polling and waiting in a work. Signed-off-by: Monk Liu Reviewed-by: Alex Deucher Reviewed-by: Xiangliang Yu Signed-off-by: Alex Deucher

drm/amdgpu:no kiq for mailbox registers access

2017-03-30T03:53:10Z

Use no kiq version reg access due to: 1) better performance 2) INTR context consideration (some routine in mailbox is in INTR context e.g.xgpu_vi_mailbox_rcv_irq) Signed-off-by: Monk Liu Reviewed-by: Alex Deucher Reviewed-by: Xiangliang Yu Signed-off-by: Alex Deucher