linux/drivers/gpu/drm/amd/amdgpu/nv.c, branch v5.10Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
https://git.shady.money/linux/atom?h=v5.102020-11-13T05:30:05Zdrm/amdgpu: enable DCN for navi10 headless SKU2020-11-13T05:30:05ZTianci.Yintianci.yin@amd.com2020-11-06T06:56:35Zurn:sha1:38a2509184952f799d465b26279ef1bd36fb8277
There is a NULL pointer crash when DCN disabled on headless SKU.
On normal SKU, the variable adev->ddev.mode_config.funcs is
initialized in dm_hw_init(), and it is fine to access it in
amdgpu_device_resume(). But on headless SKU, DCN is disabled,
the funcs variable is not initialized, then crash arises.
Enable DCN to fix this issue.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: rename nv_is_headless_sku()2020-10-30T05:16:02ZFlora Cuiflora.cui@amd.com2020-10-28T06:04:29Zurn:sha1:4f0a1c99aa9f9f000025536efa9df0c7bb6f4bba
for headless NAVI ASICs
Signed-off-by: Flora Cui <flora.cui@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: disable DCN and VCN for Navi14 0x7340/C9 SKU2020-10-30T05:15:47ZFlora Cuiflora.cui@amd.com2020-10-27T06:58:19Zurn:sha1:06a5af1f62af815d0cb201d6becf540d3742e892
Navi14 0x7340/C9 SKU has no display and video support, remove them.
Signed-off-by: Flora Cui <flora.cui@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: disable DCN and VCN for navi10 blockchain SKU(v3)2020-10-26T21:06:59ZTianci.Yintianci.yin@amd.com2020-10-22T03:40:26Zurn:sha1:a305e7dc5fa86ff9cf6cd2da30215a92d43c9285
The blockchain SKU has no display and video support, remove them.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: switch to indirect reg access helper2020-10-01T14:42:48ZHawking ZhangHawking.Zhang@amd.com2020-09-15T09:57:30Zurn:sha1:705a2b5ba0635c2fa3e5b6a830a6b4fe178de699
Switch WREG32/RREG32_PCIE to use indirect reg access
helper for soc15 and onwards
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: fix hdp register access error2020-09-22T21:37:38ZStanley.YangStanley.Yang@amd.com2020-09-22T08:56:54Zurn:sha1:78f0aef11fdee20abfd0deec2e2ae37c72406bde
mmHDP_READ_CACHE_INVALIDATE register is in HDP not in NBIO
Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Fix consecutive DPC recovery failures.2020-09-15T21:25:04ZAndrey Grodzovskyandrey.grodzovsky@amd.com2020-08-24T16:30:47Zurn:sha1:c1dd4aa624076cb6d4724fad2d9e9e71e46bbc9f
Cache the PCI state on boot and before each case where we might
loose it.
v2: Add pci_restore_state while caching the PCI state to avoid
breaking PCI core logic for stuff like suspend/resume.
v3: Extract pci_restore_state from amdgpu_device_cache_pci_state
to avoid superflous restores during GPU resets and suspend/resumes.
v4: Style fixes.
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: use MODE1 reset for navy_flounder by default2020-08-26T20:40:19ZJiansong ChenJiansong.Chen@amd.com2020-08-25T07:39:57Zurn:sha1:22dd44f47cf74c2891c359976f308941a3736605
Switch default gpu reset method to MODE1 for navy_flounder.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add pre_asic_init callback for navi2020-08-26T20:40:19ZAlex Deucheralexander.deucher@amd.com2020-08-19T21:04:47Zurn:sha1:a71737313e57a1885c5cba7e006be24cce0f27c2
Nothing to do for this family.
Acked-by: Nirmoy Das <nirmoy.das@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: note what type of reset we are using2020-08-14T21:03:20ZAlex Deucheralexander.deucher@amd.com2020-08-11T16:02:21Zurn:sha1:11043b7a995c18ea725c956825d1dfcbbdd8e78b
When we reset the GPU, note what type of reset will be
used. This makes debugging different reset scenarios
more clear as the driver may use different reset
methods depending on conditions on the system.
Acked-by: Nirmoy Das <nirmoy.das@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>