linux/drivers/gpu/drm/amd/amdgpu/nv.c, branch v5.12Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
https://git.shady.money/linux/atom?h=v5.122021-03-04T03:48:33Zdrm/amdgpu:disable VCN for Navi12 SKU2021-03-04T03:48:33ZAsher.SongAsher.Song@amd.com2021-02-24T10:41:34Zurn:sha1:0c61ac8134ffc851681ce5d4bd60d97c3d5aed27
Navi12 0x7360/C7 SKU has no video support, so remove it.
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Asher.Song <Asher.Song@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
drm/amdgpu/nv: add PCI reset support2021-02-09T20:30:01ZAlex Deucheralexander.deucher@amd.com2021-02-04T16:24:00Zurn:sha1:f172865a3632b85f29c2af9b044f4dd51581740f
Use generic PCI reset for GPU reset if the user specifies
PCI reset as the reset mechanism. This should in general
only be used for validation.
Acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: support rom clockgating related function for NV family2021-02-09T20:28:36ZLikun GaoLikun.Gao@amd.com2021-02-03T10:45:42Zurn:sha1:1001f2a1f33dfe88bc7581d0177d01e9d299999c
Add functions to support enable/disable rom clock gating and get rom
clock gating status.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: switch to use smuio callbacks for NV family2021-02-09T20:28:27ZLikun GaoLikun.Gao@amd.com2021-02-03T10:23:49Zurn:sha1:0bf7f2dcb9a65dcc9efb47e3a393108499d6a110
Switch to smuio callbacks: use smuio v11_0_6 callbacks for
Sienna_cichlid and forward ASIC, use smuio v11_0 callbacks for the
other NV family ASIC.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: support ASPM for some specific ASIC2021-02-09T20:28:04ZLikun GaoLikun.Gao@amd.com2021-02-01T06:44:09Zurn:sha1:e1edaeafeb667688125ef1c4e2a098d2c798fc24
Support to program ASPM and LTR for Sienna Cichlid and forward ASIC.
Disable ASPM for Sienna Cichlid and forward ASIC by default.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: disable gpu reset on Vangogh for now2021-01-28T19:58:10ZAlex Deucheralexander.deucher@amd.com2021-01-27T02:57:00Zurn:sha1:33cf440d594bfbf81fc20604957bc64f02d0b560
Until the issues in the SMU firmware are fixed.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
drm/amdgpu: fix mode2 reset sequence for vangogh2021-01-14T04:47:58ZAlex Deucheralexdeucher@gmail.com2020-11-25T16:21:31Zurn:sha1:b913ec628ce2e701ba5a7d5f060f4d62d7a2ce06
We need to save and restore PCI config space.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
drm/amdgpu/nv: add mode2 reset handling2021-01-14T04:47:54ZAlex Deucheralexdeucher@gmail.com2020-11-25T16:21:30Zurn:sha1:1608635534fb8cc42e94d19d52789d9448f02536
Vangogh will use mode2 reset, so plumb it through the nv
soc driver.
Acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
drm/amdgpu: switch hdp callback functions for hdp v52021-01-05T16:33:08ZLikun GaoLikun.Gao@amd.com2020-12-28T09:02:21Zurn:sha1:bf087285dcd7e553e37902c5201c50c2e65682d6
Switch to use the HDP functions which unified on hdp structure instead of
the scattered hdp callback functions.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: set mode1 reset as default for dimgrey_cavefish2020-12-16T18:27:17ZTao Zhoutao.zhou1@amd.com2020-12-15T10:04:04Zurn:sha1:15ed44c0e7129a0967157f7b349e1b3feb26a534
Use mode1 reset for dimgrey_cavefish by default.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>