linux/drivers/gpu/drm/amd/amdgpu/nv.c, branch v5.17

drm/amdgpu/sriov/vcn: add new vcn ip revision check case for SIENNA_CICHLID

2021-12-01T21:58:11Z

[WHY] for sriov odd# vf will modify vcn0 engine ip revision(due to multimedia bandwidth feature), which will be mismatched with original vcn0 revision [HOW] add new version check for vcn0 disabled revision(3, 0, 192), typically modified under sriov mode Signed-off-by: Jane Jian Reviewed-by: Guchun Chen Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu: Fix MMIO HDP flush on SRIOV

2021-11-24T20:02:25Z

Disable HDP register remapping on SRIOV and set rmmio_remap.reg_offset to the fixed address of the VF register for hdp_v*_flush_hdp. Signed-off-by: Felix Kuehling Tested-by: Bokun Zhang Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher

drm/amdgpu: add missed support for UVD IP_VERSION(3, 0, 64)

2021-11-10T17:03:41Z

Fixes: 96b8dd4423e74d ("drm/amdgpu/amdgpu_vcn: convert to IP version checking") Signed-off-by: Flora Cui Signed-off-by: Guchun Chen Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu: drop nv_set_ip_blocks()

2021-10-20T15:43:57Z

No longer used since IP enumeration is now driven by amdgpu IP discovery code. Acked-by: Evan Quan Signed-off-by: Alex Deucher

drm/amdgpu: support B0&B1 external revision id for yellow carp

2021-10-20T15:43:56Z

B0 internal rev_id is 0x01, B1 internal rev_id is 0x02. The external rev_id for B0 and B1 is 0x20. The original expression is not suitable for B1. v2: squash in fix for display code (Alex) Signed-off-by: Aaron Liu Reviewed-by: Huang Rui Signed-off-by: Alex Deucher

drm/amdgpu: convert IP version array to include instances

2021-10-04T19:23:01Z

Allow us to query instances versions more cleanly. Instancing support is not consistent unfortunately. SDMA is a good example. Sienna cichlid has 4 total SDMA instances, each enumerated separately (HWIDs 42, 43, 68, 69). Arcturus has 8 total SDMA instances, but they are enumerated as multiple instances of the same HWIDs (4x HWID 42, 4x HWID 43). UMC is another example. On most chips there are multiple instances with the same HWID. This allows us to support both forms. v2: rebase v3: clarify instancing support Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu/nv: convert to IP version checking

2021-10-04T19:22:59Z

Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu/nv: export common IP functions

2021-10-04T19:22:58Z

So they can be driven by IP dicovery table. Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: move headless sku check into harvest function

2021-10-04T19:22:58Z

Consolidate harvesting information. Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amd/display: add cyan_skillfish display support

2021-10-04T19:22:57Z

[Why] add display related cyan_skillfish files in. makefile controlled by CONFIG_DRM_AMD_DC_DCN201 flag. v2: squash in clang fixes from Harry, Nathan v3: squash in missing CONFIG_DRM_AMD_DC check (Alex) Signed-off-by: Charlene Liu Signed-off-by: Zhan Liu Reviewed-by: Charlene Liu Acked-by: Jun Lei Acked-by: Harry Wentland Acked-by: Alex Deucher Signed-off-by: Alex Deucher