linux/drivers/gpu/drm/amd/amdgpu/nv.c, branch v5.9Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
https://git.shady.money/linux/atom?h=v5.92020-08-26T19:45:51Zdrm/amdgpu: use MODE1 reset for navy_flounder by default2020-08-26T19:45:51ZJiansong ChenJiansong.Chen@amd.com2020-08-25T07:39:57Zurn:sha1:75947544c8abd380064c817e2a2f043914d49e55
Switch default gpu reset method to MODE1 for navy_flounder.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: use mode1 reset by default for sienna_cichlid2020-08-07T21:47:25ZLikun GaoLikun.Gao@amd.com2020-08-06T09:37:28Zurn:sha1:f2e2573c0823c07dc8aac4a8e0947881af2340bd
Swith default gpu reset method for sienna_cichlid to MODE1 reset.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: expand sienna chichlid reg access support2020-08-06T20:23:20ZJohn Clementsjohn.clements@amd.com2020-07-22T01:40:11Zurn:sha1:ebfbd1c2ca02f1c1bc9f8f0a7783e71efb57e4cc
Added dedicated 64bit reg read/write support
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: enable xgmi support for sienna cichlid2020-07-21T19:37:39ZJohn Clementsjohn.clements@amd.com2020-07-17T06:13:50Zurn:sha1:c652923afa7c8fef2aee42142e9663c0e69f367d
set xgmi support flag suring nv ip init sequence
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: enable ih CG for navy_flounder2020-07-15T17:27:34ZJiansong ChenJiansong.Chen@amd.com2020-07-08T11:02:14Zurn:sha1:85e7151baa2ffc76edd9a0267caffd369ab6cd93
Enable ih CG by setting the corresponding flag.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: enable hdp CG and LS for navy_flounder2020-07-15T17:27:34ZJiansong ChenJiansong.Chen@amd.com2020-07-08T10:59:11Zurn:sha1:4759f8871f3dc75a47b0b9cf38064958ce76eb35
Enable hdp CG and LS by setting the corresponding flags.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: enable mc CG and LS for navy_flounder2020-07-15T17:27:34ZJiansong ChenJiansong.Chen@amd.com2020-07-08T10:53:36Zurn:sha1:92c737561c526ea7fbb87b52244b9fb1e914ff8f
Enable mc CG and LS by setting the corresponding flags.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: enable athub/mmhub PG for navy_flounder2020-07-15T17:27:34ZJiansong ChenJiansong.Chen@amd.com2020-07-08T10:42:04Zurn:sha1:47fc894a8711e9cc22bc3c508d15415c0b191480
Enable athub/mmhub PG by setting the corresponding flags.
Actually the enablement is exercised by PMFW.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: add DC support for navy flounder2020-07-15T17:27:26ZBhawanpreet LakhaBhawanpreet.Lakha@amd.com2020-07-08T21:11:12Zurn:sha1:a6c5308f2a7ad2a79fb6fd60b52367c51434c04a
Plumb DC support for navy flounder through.
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: enable GFX clock gating for navy_flounder2020-07-15T16:47:21ZJiansong ChenJiansong.Chen@amd.com2020-07-02T07:34:37Zurn:sha1:40582e670feb27656ac0d95f0ff0b2bf2414d63e
Enable GFX MGCG, CGCG and 3DCG for navy_flounder.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>